Part Number: TMDSEVM437X

Hi Renan,

Issue: I am trying to integrate Microchip's WILC1000 wifi device with TI Sitara AM437x EVM board using SPI interface. I am using the latest SDK with kernel version 4.19.38. I am using SPI pins which is projected in the J30 connector, which is on the back side of the board. I have configured the SDK kernel for the EVM board and added WILC driver under driver/staging/wilc1000 and generated the spi module(wilc-spi.ko). I have edited the am437x-gp-evm.dts file to add the spi node and generated the dtb file and then replaced the existing zImage and dtb file in the sd card with the latest build image and dtb and board got booted up successfully.

When I try to load the spi module using "insmod wilc-spi.ko" command. I am facing spi failure.

Logs: Made a zip file and added all the below logs. Find it in the attachment

Kernel logs:Kernel_log Am437x-gp-evm.
dts file: am437x-gp-evm_dts Am4372.
dtsi : am4372_dtsi
Wilc driver load log: wilc_log
Logic Analyzer SPI probe: SPI_probe

In the SPI probe image in the attachment:
Channel 0: SCK
Channel 1: MOSI
Channel 2: MISO
Channel 3: Slave Select
Channel 4: Chip_enable
Channel 5: IRQ
Channel 6: RESET
(Please visit the site to view this file)Basically, as per the proper working WILC1000 device SPI probing, My CHIP_EN and RESET, IRQ should be HIGH in the beginning and IRQ should be toggle low when interrupt occur

DTS file configuration
spi1_pins_default: spi1_pins_default {
pinctrl-single,pins = < AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) / (N24) mcasp0_aclkx.spi1_sclk /
AM4372_IOPAD(0x994, PIN_OUTPUT_PULLUP | MUX_MODE3) / (N22) mcasp0_fsx.spi1_d0 /
AM4372_IOPAD(0x998, PIN_INPUT_PULLUP | MUX_MODE3) / (H23) mcasp0_axr0.spi1_d1 /
AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) / (M24) mcasp0_ahclkr.spi1_cs0 /
>;
};
interrupt_pins: interrupt_pins {
pinctrl-single,pins = <
AM4372_IOPAD(0xa54, PIN_OUTPUT_PULLUP | MUX_MODE7) / (R24) spi4_d0.gpio5[5] /
AM4372_IOPAD(0xa40, PIN_OUTPUT_PULLUP | MUX_MODE7) / (G20) gpio5_10.gpio5[10] /
AM4372_IOPAD(0xa44, PIN_OUTPUT_PULLUP | MUX_MODE7) / (F23) gpio5_11.gpio5[11] /
>;
};
};
&spi1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_default>;
pinctrl-1 = <&interrupt_pins>;
wilc_spi@0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
compatible = "microchip,wilc1000";
reg = <0>;
spi-max-frequency = <16000000>;
interrupt-parent = <&gpio5>;
irq-gpios = <&gpio5 5 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
chip_en-gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>;
};
};
Loading the driver is giving SPI error.
1) There is no data in the MOSI line.
2) Clock is as per the the clock frequency set in spi node
3) There is some random data in MISO
4) Slave select pins is proper(High in the beginning and then getting low)
5) Chip_en pin is staying as LOW. Not able to configure is a HIGH
6) Interrupt pin is staying HIGH
7) RESET Pin is togglling As the initial step I need to make the chip_enable pin as HIGH. Thus the WILC1000 device will get initialized. And other issue is there is no data on MOSI
can you check and let me know what I am doing wrong in my setting in dts file

Part Number: TDA2HG

I hope to achieve the function of DVR.DVR is to save the video of four camera on the SD card.So i hope to know whether there is suitable links or usecases to encode the video and write it on the SD card in the SDK.

Part Number: PROCESSOR-SDK-AM65X

Tool/software: Code Composer Studio

Hi all,

I am currently developing and working on the Gatewayapplication example project provided with Processor SDK RTOS for AM65x. I created a CCS project for the R5F core, imported the source code and got the application to build succesfully from there by linking in the neccesary component and driver libraries.. I am using the TI compiler. The application however does not want to upload to the development board from CCS, and I think this might have to do with the linker and compiler.

Should the GNU compiler or TI compiler be used for this application?

If the GNU compiler should be used, is there an example project for CCS (not from command line) somewhere on the SDK where the R5F core uses the GNU compiler? (A SYSBIOS project is not able to be selected for the R5 core using the GNU compiler, only a basic project) I would like to be able to take a look at these project settings in order to possibly get the gatewayapp to build successfully from within CCS and to upload successfully onto the development board.

When building the project from the command line, it does seem however that the TI compiler is used. If the TI compiler should be used, is there still an example project for the R5F core somewhere I can reference?

I hope my question is clear, otherwise let me know. I look forward to hearing from you.

Regards,

Johnny

Part Number: AM3354

Linux 4.19 CPSW driver

Can anyone point to the code in cpsw.c/phy.c where the link detection is done of a device under cpsw's control? I do not see an interrupt, so I assume it is being polled by the phy_state_machine in phy.c....

I want to add the link detection of port 2 (second port of my switch) to work as as well as port 1 (port 1 on my 2 port switch) and port 5 (my mac/phy chip) which both work great.

I have already tried to fool the switch phy driver to report link = on, but it only works AFTER the cable is really connected - then you can remove it and it stays linked so the second port will function without port 1 having a cable plugged in.

Thanks

Part Number: TDA2PXEVM

Tool/software: Code Composer Studio

Hi, everybody

I wrote a program about getting the temperature, voltage, and frequency of the CPU core. The program included APIs are obtained in the example of the SDK-PDK-PM module (clkrate_manager/ina226_power_measure/junction_temp_sensor), and files such as Makefile are also configured. Compile the executable file(.xem4) under cmd.

However, when running on CCS, it always prompts that the source file cannot be found, and there are many places that will prompt this when running in a single step.

Can't find a source file at "  ...  " 

Locate the file or edit the source lookup path to include its location

The 'source files' of each local prompt are different. Moreover, the first step in the single-step execution is directly executed into a strange source program, and is not executed in the order of my main() function. What is the situation like this? Is the program I wrote not modifying a certain file and causing this series of problems?

Please help me, these problems have been bothering me for many days.

Thanks very much!!

Part Number: DRA726

Tool/software: TI C/C++ Compiler

Dear Team,

My customer use VSDK0305(linux), They need to boot IPU1-0 from uboot. (IPU1 firmware is theirs.). I already request them to add .resource table. Now they already can  download the image from uboot,.but they can not boot. I let customer to try. modified the PC point to 0x9e in CCS and can run to Main.

uboot log as below:

This picture's IPU1 address is not correct, because we download the image to 0x9e000000. Our image:

Customer image:

Please help to give some comments or suggestions about the issue? and how to configure the entry point address.

Best Regards,

Fredy

Part Number: TDA2EVM5777

HI

Part Number: AM5718

Tool/software: Code Composer Studio

Hi,

I want to change default interrupt mapping of particular peripherals.How we change default interrupt mapping. TRM does not provide enough information about that(for core MPU).

Part Number: TDA2P-ACD

As this is a new topic, moving to a new e2e thread from the following https://e2e.ti.com/support/processors/f/791/t/827092

Per Gokul:  "We are facing some crash issue during one of our test-case scenario. ( CAN disconnect).

 During CAN disconnect , system is freezed.

 We are expecting normal behavior of the system, even when there is no CAN data. (Camera & display should not be freezed)

 I see below error when I connect the CAN again

 [IPU1-0]   3306.653053 s: UTILS: MBX: Utils_mbxSendCmd(): Msg Alloc Failed (0)!!!

[IPU1-0]   3306.662447 s: UTILS: MBX: Utils_mbxSendCmd(): Msg Alloc Failed (0)!!!

 I need system support in solving this issue. 

Hi, This is LG electronics engineer. 

I have a couple of question for PSDKRA_RTOS(v0.9).

Testing the CAN profile application within MCUSW of  PSDKRA_RTOS(v0.9) in J721EXCP01EVM(Board).

1. In order to configure MCAL every configuration for testing this application, should I use the EB configurator ? 

It is just one solution for configuring MCAL ?

If i should use the EB configurator, there is no installation guide which can follow in PSDKRA_RTOS(v0.9). 

Also, this version's MCAL modules aren't delivered in the form of EBtresos plugins.

2. I see your every test report, you seem to just test "CAN example application" in csl folder through building and compiling the BAREMETAL type.

If i use the CAN example application, it is easy to execute this application through JTAG tool. However, because of some problem, we can't use JTAG.

We have to execute the CAN profile application in MCUSW.

In MCUSW, there is your test report. Is it tested through tirtos building version that some data is transmitted to external CANoe and received from CANoe through CAN communication ? 

3. When i execute your CAN profile application, CANoe tool can't receive any data from your EVM.  I was debugging it that can you give me a few advice such as using EB configurator etc. ?

Part Number: AM5718

Tool/software: Linux

Hello

I am using am5718idk with linux on ARM and TI-RTOS on dsp processor.
I have to access pru-ethenet from dsp and all other processor(ipu1 and ipu2) are not used.
I have assigned 152MB memory for DSP instead for 64MB already in device tree.
I have modified the reserved memory in DTS file
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
};

reserved-memory {
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;

ipu2-memory@95800000 {
compatible = "shared-dma-pool";
reg = <0x0 0x95800000 0x0 0x3800000>;
reusable;
status = "disabled";
phandle = <0xc4>;
};

dsp1-memory@0x95800000 {
compatible = "shared-dma-pool";
reg = <0x0 0x95800000 0x0 0x9800000>;
reusable;
status = "okay";
phandle = <0xca>;
};

ipu1-memory@9d000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x9d000000 0x0 0x2000000>;
reusable;
status = "disabled";
phandle = <0xbd>;
};

cmem_block_mem@a0000000 {
reg = <0x0 0xa0000000 0x0 0xc000000>;
no-map;
status = "okay";
phandle = <0x131>;
};
};
I have also modified the memory map of the Ti-RTOS file to fit in this memory range(0x95800000 0x0 0x9800000>;) and tested independently
while loading the DSP image from linux following error is comming
root@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# echo 40800000.dsp > unbind
[10098.211292] remoteproc remoteproc2: releasing 40800000.dsp
root@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# echo 40800000.dsp > bind
[10136.981421] omap-rproc 40800000.dsp: assigned reserved memory node dsp1-memory@99000000(already in orginal map)
[10136.995642] remoteproc remoteproc2: 40800000.dsp is available
[10137.002835] remoteproc remoteproc2: Direct firmware load for dra7-dsp1-fw.xe66 failed with error -2
root@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# [10137.015043] remoteproc remoteproc2: powering up 40800000.dsp
[10137.026850] remoteproc remoteproc2: Direct firmware load for dra7-dsp1-fw.xe66 failed with error -2
[10137.037307] remoteproc remoteproc2: request_firmware failed: -2

Even though I have modified the memory range used by the DSP in device tree,error log showing no change in the default memory map

Regards

Satheesh KumarS

Part Number: TMDXIDK57X-LCD

Hello every one,

I'm trying to use messageQ module between Cortex A15 core1 and C66x DSP1 , But I'm stuck in IPC initializations, I'm using AM5728 IDK, here is my main.c for cortex a15:

#include <xdc/std.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>



#include <ti/ipc/Ipc.h>
#include <ti/ipc/MessageQ.h>
#include <ti/ipc/MultiProc.h>
#include <ti/sdo/ipc/interfaces/ITransport.h>
#include <ti/sdo/ipc/interfaces/IMessageQTransport.h>

#define SERVER "DSP1"


Void taskFxn(UArg a0, UArg a1)
{
    Int     status;
    UInt16  remoteProcId;


    /*
     *  initialize the ipc layer
     */
    status = Ipc_start();
    System_printf("Ipc_start: %d", status);
    System_flush();
    if (status < 0) {
        System_abort("Ipc_start failed\n");
    }

    remoteProcId = MultiProc_getId(SERVER);
    System_printf("remoteProcId: %d", remoteProcId);
    System_flush();
    if (remoteProcId == MultiProc_INVALIDID) {
        System_abort("Improper MultiProc ID\n");
    }
    do {
        status = Ipc_attach(remoteProcId);

    } while ((status < 0) && (status == Ipc_E_NOTREADY));
    System_printf("Ipc_attach: %d", status);
    System_flush();

}

/*
 *  ======== main ========
 */
Int main()
{ 
    Task_Handle task;
    Error_Block eb;

    System_printf("enter main()\n");

    Error_init(&eb);
    task = Task_create(taskFxn, NULL, &eb);
    if (task == NULL) {
        System_printf("Task_create() failed!\n");
        BIOS_exit(0);
    }

    BIOS_start();    /* does not return */
    return(0);
}

and this is *.cfg file:

var Defaults = xdc.useModule('xdc.runtime.Defaults');
var Diags = xdc.useModule('xdc.runtime.Diags');
var Error = xdc.useModule('xdc.runtime.Error');
var Log = xdc.useModule('xdc.runtime.Log');
var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
var Main = xdc.useModule('xdc.runtime.Main');
var Memory = xdc.useModule('xdc.runtime.Memory')
var SysMin = xdc.useModule('xdc.runtime.SysMin');
var System = xdc.useModule('xdc.runtime.System');
var Text = xdc.useModule('xdc.runtime.Text');
System.extendedFormats = '%$L%$S%$F%f';
var BIOS = xdc.useModule('ti.sysbios.BIOS');
var Clock = xdc.useModule('ti.sysbios.knl.Clock');
var Swi = xdc.useModule('ti.sysbios.knl.Swi');
var Task = xdc.useModule('ti.sysbios.knl.Task');
var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');

System.maxAtexitHandlers = 4;       

BIOS.heapSize = 0x1000;

/*
 * Build a custom SYS/BIOS library from sources.
 */
BIOS.libType = BIOS.LibType_Custom;

/* System stack size (used by ISRs and Swis) */
Program.stack = 0x2000;

/* Circular buffer size for System_printf() */
SysMin.bufSize = 0x200;

/* 
 * Create and install logger for the whole system
 */
var loggerBufParams = new LoggerBuf.Params();
loggerBufParams.numEntries = 16;
var logger0 = LoggerBuf.create(loggerBufParams);
Defaults.common$.logger = logger0;
Main.common$.diags_INFO = Diags.ALWAYS_ON;

System.SupportProxy = SysMin;
var SemiHostSupport = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');




/*========================   IPC  =======================*/

xdc.useModule('ti.sdo.ipc.Ipc');
xdc.useModule('ti.sdo.ipc.MessageQ');
xdc.useModule('ti.sdo.ipc.SharedRegion');
xdc.useModule('ti.sdo.utils.MultiProc');
xdc.useModule('ti.sysbios.heaps.HeapBuf');




/* configure processor names */
var procNameAry = ["DSP1","DSP2","IPU1","IPU2",
        "HOST"];
var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
MultiProc.setConfig("HOST", procNameAry);

/* ipc configuration */
var Ipc = xdc.useModule('ti.sdo.ipc.Ipc');
Ipc.procSync = Ipc.ProcSync_PAIR;
Ipc.sr0MemorySetup = true;

/* shared region configuration */
var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');

/* configure SharedRegion #0 (IPC) */
var SHAREDMEM      = 0x8E000000;
var SHAREDMEMSIZE  = 0x1000000;


SharedRegion.setEntryMeta(0,
    new SharedRegion.Entry({
        name:           "mySharedRegion",
        base:           SHAREDMEM,
        len:            SHAREDMEMSIZE,
        ownerProcId:    0,
        isValid:        true,
        cacheEnable:    true
    })
);





/* create a default heap */
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var heapMemParams = new HeapMem.Params();
heapMemParams.size = 0x8000;

var Memory = xdc.useModule('xdc.runtime.Memory');
Memory.defaultHeapInstance = HeapMem.create(heapMemParams);

and this is my project folder:

(Please visit the site to view this file)

I debugged both cores and they both stick in while loop and Ipc_attach returns -11, I think there is something wrong with the sharedRegion but I can't figure it out, I searched the forum, similar resolved questions didn't help so much.

I'm using ti-RTOS on both cores and these are my SW/tools versions;

bios_6_75_02_00,

ccs910,

ipc_3_50_03_05,

xdctools_3_51_01_18,

processor_sdk_rtos_am57xx_6_00_00_07,

B.R,

Alex.

Part Number: TDA2E

Hi,

     I have some question on TDA2E's application.

    function block as below:

1. In this way, 960 has two CSI outputs, each of which is 4lane, but the input of my 960's 4-way camera is different. Now SOC has only 6lane. How to do it?

2. What's more, whether TDA2E can satisfy the video processing ability of four cameras alone?

thanks.

Part Number: AM6548

Hello,

We use the AM654x IDK Board with processor_sdk_rtos_am65xx_5_03_00_07. In our user case, we only need one ARM Cortex R5F core. To save power we have to disable the other unused cores of the processor.

When we load the sysfw.bin File in the SBL during bootup all cores and modules get powered up. We tried to shutdown modules with Sciclient_pmSetModuleState(..) in the SBL File and with PMLIBSysConfigSetPowerState(..) in a C – Program, but if we read back the current state, all modules are still powered on.

Is it possible to deactivate the unused cores with a function in the SBL code, or should the sysfw.bin be reconfigured?

Is the source code of the SYS Firmware available?

Best Regards

Marco

Hi,

We design a board with two ethernet-phy interfaces (eth0: Marvell 88E1518 in RGMII mode and eth1: DP83848 in RMII mode).

For now, I can only change the active slave at compile time in the devicetree.

By default,  I have ethact=ethernet@4a100000 and if I change it to either eth0 or eth1 with setenv it doesn't switch the port.

This is my config for now:

In the dts:

&mac {
  pinctrl-names = "default", "sleep";
  pinctrl-0 = <&cpsw_default>;
  pinctrl-1 = <&cpsw_sleep>;
  dual_emac;
  active_slave = <0>;
  status = "okay";
};

&davinci_mdio {
  pinctrl-names = "default", "sleep";
  pinctrl-0 = <&davinci_mdio_default>;
  pinctrl-1 = <&davinci_mdio_sleep>;
  status = "okay";
};

&cpsw_emac0 {
  phy_id = <&davinci_mdio>, <0>;
  phy-mode = "rgmii-txid";
  dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
  phy_id = <&davinci_mdio>, <1>;
  phy-mode = "rmii";
  dual_emac_res_vlan = <2>;
};

&phy_sel {
  rmii-clock-ext;
};

cpsw_default: cpsw_default {
    pinctrl-single,pins = <
      /* Slave 1 */
      0x114 (PIN_OUTPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE2) /* (J16) gmii1_txen.rgmii1_tctl */
      0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)                  /* (J17) gmii1_rxdv.rgmii1_rctl */
      0x11c (PIN_OUTPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE2) /* (J18) gmii1_txd3.rgmii1_td3 */
      0x120 (PIN_OUTPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE2) /* (K15) gmii1_txd2.rgmii1_td2 */
      0x124 (PIN_OUTPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE2) /* (K16) gmii1_txd1.rgmii1_td1 */
      0x128 (PIN_OUTPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE2) /* (K17) gmii1_txd0.rgmii1_td0 */
      0x12c (PIN_OUTPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE2) /* (K18) gmii1_txclk.rgmii1_tclk */
      0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)                  /* (L18) gmii1_rxclk.rgmii1_rclk */
      0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)                  /* (L17) gmii1_rxd3.rgmii1_rd3 */
      0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)                  /* (L16) gmii1_rxd2.rgmii1_rd2 */
      0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)                  /* (L15) gmii1_rxd1.rgmii1_rd1 */
      0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)                  /* (M16) gmii1_rxd0.rgmii1_rd0 */
      /* Slave 2 */
      0x64 (PIN_INPUT_PULLUP | MUX_MODE3)       /* (U16) gpmc_a9.rmii2_crs_dv */
      0x74 (PIN_INPUT_PULLUP | MUX_MODE3)       /* (U17) gpmc_wpn.rmii2_rxer */
      0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* (R13) gpmc_a0.rmii2_txen */
      0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* (V15) gpmc_a5.rmii2_txd0 */
      0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* (R14) gpmc_a4.rmii2_txd1 */
      0x6c (PIN_INPUT_PULLUP | MUX_MODE3)       /* (V17) gpmc_a11.rmii2_rxd0 */
      0x68 (PIN_INPUT_PULLUP | MUX_MODE3)       /* (T16) gpmc_a10.rmii2_rxd1 */
      0x108 (PIN_INPUT_PULLUP | MUX_MODE1)      /* (H16) mii1_col.rmii2_refclk */
    >;
  };

  cpsw_sleep: cpsw_sleep {
    pinctrl-single,pins = <
      /* Slave 1 reset value */
      0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      /* Slave 2 reset value */
      0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
    >;
  };

  davinci_mdio_default: davinci_mdio_default {
    pinctrl-single,pins = <
      /* MDIO */
      0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* (M17) mdio_data.mdio_data */
      0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                 /* (M18) mdio_clk.mdio_clk */
    >;
  };

  davinci_mdio_sleep: davinci_mdio_sleep {
    pinctrl-single,pins = <
      /* MDIO reset value */
      0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
      0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
    >;
  };

In the board.c:

static struct cpsw_slave_data cpsw_slaves[] = {
    {
        .slave_reg_ofs    = 0x208,
        .sliver_reg_ofs    = 0xd80,
        .phy_addr    = 0,
        .phy_if        = PHY_INTERFACE_MODE_RMII,
    },
    {
        .slave_reg_ofs    = 0x308,
        .sliver_reg_ofs    = 0xdc0,
        .phy_addr    = 1,
        .phy_if        = PHY_INTERFACE_MODE_RGMII,
    },
};

static struct cpsw_platform_data cpsw_data = {
    .mdio_base        = CPSW_MDIO_BASE,
    .cpsw_base        = CPSW_BASE,
    .mdio_div        = 0xff,
    .channels        = 8,
    .cpdma_reg_ofs        = 0x800,
    .slaves            = 2,
    .slave_data        = cpsw_slaves,
    .ale_reg_ofs        = 0xd00,
    .ale_entries        = 1024,
    .host_port_reg_ofs    = 0x108,
    .hw_stats_reg_ofs    = 0x900,
    .bd_ram_ofs        = 0x2000,
    .mac_control        = (1 << 5),
    .control        = cpsw_control,
    .host_port_num        = 0,
    .version        = CPSW_CTRL_VERSION_2,
};

int board_eth_init(bd_t *bis)
{
    int rv, n = 0;

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
    (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))

#ifdef CONFIG_DRIVER_TI_CPSW
    // set eth0 in rgmii1 with internal delay
    writel((GMII1_SEL_RGMII | RGMII1_IDMODE), &cdev->miisel);
    // set eth1 in rmii2 with refclk2 as input
    writel((GMII2_SEL_RMII | RMII2_IO_CLK_EN), &cdev->miisel);
    }

    rv = cpsw_register(&cpsw_data);
    if (rv < 0)
        printf("Error %d registering CPSW switch\n", rv);
    else
        n += rv;
#endif

#endif
    return n;
}

In U-Boot:

When I compile U-boot with active_slave=<0>

=> mdio list
ethernet@4a100000:
0 - Generic PHY <--> ethernet@4a100000

When I compile U-boot with active_slave=<1>

=> mdio list
ethernet@4a100000:
1 - Generic PHY <--> ethernet@4a100000

=> mii info
PHY 0x00: OUI = 0x5043, Model = 0x1D, Rev = 0x01, 100baseT, HDX
PHY 0x01: OUI = 0x80017, Model = 0x09, Rev = 0x00,  10baseT, HDX

=> ping 192.168.0.1    
link up on port 1, speed 100, full duplex
Using ethernet@4a100000 device
host 192.168.0.1 is alive

Can somebody tell me why I can only change the active_slave at compile time and not with ethact or ethprime at runtime ? Am I missing something ?

I have few other questions since I am beginner for ethernet questions in u-boot:

- Should I be able to see both port when typing "mdio list" ?

- Is it possible to have an ip address for each port or do they share the same ip (ipaddr) ?

- Is it possible to have both port up and working at the same time ?

Thank you !

Loïc

Part Number: TDA2EVM5777

Hi,

i am running simple use case

capture  -> alg_plugin( EVE1)  -> display

Output of this given to DLP through HDMI.

Output frame resolution is 1152*576.

I am getting below error while connecting to DLP through HDMI .

" Error Code : source error (0x2A2) - external source parallel port pixel clock frequency is not within the allowable range"

However i am trying to print "pixelClock" from "DisplayCtrlLink_drvSetConfig" function from file "displayCtrlLink_drv.c", but i am getting pixelClock as zero.

Please, let me know from where i can configure pixelClock frequency and to what value, so that can achieve proper result.

Regards,

Siva Naga

Part Number: TMDSICE3359

The TMDSICE3359 demo board file that is referenced on the website is unfortunately in the binary file format (.brd).

Is it possible to get an ASCII format of this PCB?

An ASCII file format would allow those wanting to use the demo board as a base for their own design to import the design into most of the popular PCB design software packages.

Part Number: AM5718

Hello

I am using am5718idk with linux on ARM and TI-RTOS on dsp processor.
I have to access pru-ethenet from dsp and all other processor(ipu1 and ipu2) are not used.
I have assigned 152MB memory for DSP instead for 64MB already in device tree.
I have modified the reserved memory in DTS file
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
};

reserved-memory {
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;

ipu2-memory@95800000 {
compatible = "shared-dma-pool";
reg = <0x0 0x95800000 0x0 0x3800000>;
reusable;
status = "disabled";
phandle = <0xc4>;
};

dsp1-memory@0x95800000 {
compatible = "shared-dma-pool";
reg = <0x0 0x95800000 0x0 0x9800000>;
reusable;
status = "okay";
phandle = <0xca>;
};

ipu1-memory@9d000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x9d000000 0x0 0x2000000>;
reusable;
status = "disabled";
phandle = <0xbd>;
};

cmem_block_mem@a0000000 {
reg = <0x0 0xa0000000 0x0 0xc000000>;
no-map;
status = "okay";
phandle = <0x131>;
};
};
I have also modified the memory map of the Ti-RTOS file to fit in this memory range(0x95800000 0x0 0x9800000>;) and tested independently
while loading the DSP image from linux following error is comming
root@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# echo 40800000.dsp > unbind
[10098.211292] remoteproc remoteproc2: releasing 40800000.dsp
root@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# echo 40800000.dsp > bind
[10136.981421] omap-rproc 40800000.dsp: assigned reserved memory node dsp1-memory@99000000(already in orginal map)
[10136.995642] remoteproc remoteproc2: 40800000.dsp is available
[10137.002835] remoteproc remoteproc2: Direct firmware load for dra7-dsp1-fw.xe66 failed with error -2
root@am57xx-evm:/sys/bus/platform/drivers/omap-rproc# [10137.015043] remoteproc remoteproc2: powering up 40800000.dsp
[10137.026850] remoteproc remoteproc2: Direct firmware load for dra7-dsp1-fw.xe66 failed with error -2
[10137.037307] remoteproc remoteproc2: request_firmware failed: -2

Even though I have modified the memory range used by the DSP in device tree,error log showing no change in the default memory map

Regards

Satheesh KumarS

Part Number: AM3352

Hi,

I'm asking this question on behalf of my customer.

"

I have  question about GPIO drive ability, my project use am3352, have EMMC/SD/DDR3/dual-Ethernet and use most of pings.

I have 12 LEDs to indicate system status. drive current for each LED is about 3mA, I plan to use 12 GPIO to drive those 12 LEDs.

Is it OK for AM3352 to drive those 12 LEDs? Which is better: High (drive) or Low (sink) active?

"

My initial thoughts are that he should be fine with the amount of current since the maximum current that can be driven in each GPIO pin is 6mA, but I'm not sure whether high or low is better.

Thanks!
Lauren

I have installed SimpleLink SDK 3.30 (or any other SDK version that requires the IAR EW for Arm 8.32) and now I see the warning “SYS/BIOS ROV session manager failed - can't find a JVM” whenever I start the debugger. I also don't have the menu TI-RTOS in the debugger menu bar. What does the warning mean and how can I fix it?