Part Number: AM3359
Tool/software: Code Composer Studio
Hi,
I'm using BIOS 6.72.2, NDK 3_60_00_3 and PDKam335x_1_0_15.
I can open a server connection without issue and echo data back to the client, however, if the client closes the connection how do I get the status of the connection? I tried looking at the error code for NDK_recv and it the same code regardless of data not being received or connection is closed.
Thanks in advance!
Rob
Part Number: TMS320C5535
My customer is migrating to the TMS320C5535eZdsp and had some questions:
1. It seems that currently the eZdsp chip TMS320C5535eZdsp and corresponding CC's are only supported on Windows 10, but we use Macs. Does TI have a CCS version that works with the current chip?
2. Is there a tutorial for using AIC3204 on C5535eZdsp? We found a tutorial for the TMS320C5505 USB Stick. The tutorial is downloaded from a link offered on this Wiki page:
http://processors.wiki.ti.com/index.php/Porting_C5000_Teaching_ROM_to_C5535_eZdsp .
The Author of this wiki page offer a simple solution of applying code of C5505 on C5535. But the solution needs to use libraries of C5505 instead of C5535.
We also found some simple example code on github that could help get started with audio on C5535eZdsp, but a more professional tutorial would be helpful.
Thanks!
Part Number: AM5718
Tool/software: Linux
Hi,
SDK : ti-processor-sdk-linux-rt-am57xx-evm-05.00.00.15
Toolchain : ARM GCC 8.3 2019.03 hard-float toolchain
u-boot : u-boot-2018.01
-----------------------------------------------------------------------------------
The following problems occur when compiling the boot loader.
Do you know the cause?
LD lib/built-in.o
LD u-boot
/toolchain/bin/arm-linux-gnueabihf-ld.bfd: cmd/built-in.o: in function `print_cpu_list':
/sanion/RGBTest/bsp/u-boot-2018.01/cmd/cpu.c:35: undefined reference to `cpu_get_desc'
/toolchain/bin/arm-linux-gnueabihf-ld.bfd: /sanion/RGBTest/bsp/u-boot-2018.01/cmd/cpu.c:40: undefined reference to `cpu_get_info'
make[1]: *** [Makefile:1261: u-boot] error 1
make[1]: directory '/sanion/RGBTest/bsp/u-boot-2018.01' out
make: *** [Makefile:77: boot] error 2
Part Number: TDA3XEVM
Tool/software: Code Composer Studio
Hi Expert,
I'm running PROCESSOR SDK VISION v03.04.00 rtos on tda3x custom board.
Enabled DCAN_INCLUDE in cfg.mk.
Tda3x load using CCS, the console logs is correct at run the core.
But Sending dcan to tda3x continuously at startup will cause an error.
(PC tx → tda3x rx)
See below:
Could you please provide some guide on these questions?
Thanks in advance.
Part Number: AM5718
Hi, I just realized that there are a couple of DDR signals have different ball reset state and reset release state between AM5718 and AM5728. For example, ddr1_cke on AM5718 is PU, drive 1 vs AM5728 PD , drive 0.
Will those different ball state impact the DDR circuit design which aims at a compatible design between the AM5728 and AM5718?
Another question on signal ddr_cke, there is 4.7KOHM pull down resistor on AM5728 GP EVM, but not on AM5718 IDK EVM, does this resistor a must for AM5718 as well?
Part Number: AM3352
Hi :
We use SDK 05.03.00.07 to test USB speed. Use the following instructions:
hdparm -t /dev/sda1
The test results are as follows：
When we fixed the CPU frequency to 800M，the speed is stable at 12MB/sec ：
# hdparm -t /dev/sda1
/dev/sda1:
Timing buffered disk reads: 38 MB in 3.02 seconds = 12.59 MB/sec
# hdparm -t /dev/sda1
/dev/sda1:
Timing buffered disk reads: 38 MB in 3.02 seconds = 12.59 MB/sec
# hdparm -t /dev/sda1
/dev/sda1:
Timing buffered disk reads: 38 MB in 3.06 seconds = 12.42 MB/sec
But when we use SDK 03.01.00.06 and CPU frequency is not fixed, the speed is stable at 16MB/sec.
# hdparm -t /dev/sda1
/dev/sda1:
Timing buffered disk reads: 50 MB in 3.00 seconds = 16.65 MB/sec
# hdparm -t /dev/sda1
/dev/sda1:
Timing buffered disk reads: 50 MB in 3.09 seconds = 16.19 MB/sec
# hdparm -t /dev/sda1
/dev/sda1:
Timing buffered disk reads: 50 MB in 3.01 seconds = 16.61 MB/sec
# hdparm -t /dev/sda1
/dev/sda1:
Timing buffered disk reads: 50 MB in 3.09 seconds = 16.20 MB/sec
Hi,
I have an issue while compiling kernel sources. Actually, i did clean and then tried to rebuild the kernel. I am working on DRA71X and SDK 3.04. When I tried to build, issuing command "bitbake -c compile -f linux-ti-staging" I got this below error:
WARNING: linux-ti-staging-4.4.45+gitAUTOINC+89944627d5-r1a.arago5 do_fetch: Failed to fetch URL git://git.omapzoom.org/kernel/omap;protocol=git;branch=p-ti-lsk-linux-4.4.y-next, attempting MIRRORS if available
ERROR: linux-ti-staging-4.4.45+gitAUTOINC+89944627d5-r1a.arago5 do_fetch: Fetcher failure: Fetch command failed with exit code 128, output:
Cloning into bare repository '/mnt/yocto/yocto_repo/downloads/git2/git.omapzoom.org.kernel.omap'...
fatal: read error: Connection reset by peer
ERROR: linux-ti-staging-4.4.45+gitAUTOINC+89944627d5-r1a.arago5 do_fetch: Function failed: Fetcher failure for URL: 'git://git.omapzoom.org/kernel/omap;protocol=git;branch=p-ti-lsk-linux-4.4.y-next'. Unable to fetch URL from any source.
ERROR: Logfile of failure stored in: /mnt/yocto/yocto_repo/build/arago-tmp-external-linaro-toolchain/work/delphi_jlr_isp_proto-linux-gnueabi/linux-ti-staging/4.4.45+gitAUTOINC+89944627d5-r1a.arago5/temp/log.do_fetch.59891
ERROR: Task 0 (/mnt/yocto/yocto_repo/sources/meta-ti/recipes-kernel/linux/linux-ti-staging_4.4.bb, do_fetch) failed with exit code '1'
Please help with this.
regards,
Harish.
Part Number: AM5728
Tool/software: Linux
Hi,
I would like to know where to modify the contents of the device tree of the TMDSEVM572X evaluation board.
The TMDSEVM572X evaluation board is am57xx-evm-reva3.dtb when passed to the kernel. But sdk is missing am57xx-evm-reva3.dts What should I look at?
Part Number: 66AK2L06
Tool/software: Code Composer Studio
Hello ALL,
I am working on message queue, I am currently working on DSP to DSP communication i.e. I am using two DSP cores. I am creating the message queue in DSP 1 i.e. core 0 and I am trying it open it in core 1 DSP 2
but I am facing a problem while opening it is entering into loop.
Please help in this.
Thank you
Part Number: AM5718
Tool/software: TI C/C++ Compiler
Hi
I'm using the AM5718 sitara processor and sysbios (V6.73.0.12)
Between A15 core and C66 core i'm using IPC (V3.50.2.02) for data exchange.
On C66 critical hardware interrupts are running, triggerd by the epwm1 module.
I often see interrupt delays of up to 2.5us (pwm event to code execution within interrupt),
which is too much for me.
I have set a breakpoint to high delays. Every time it triggers a looked at the calling stack of
the preempted task (in the ROV viewer). Regardless of which task is preempted the tasks
are always in "ti_sdo_ipc_notifyDrivers_NotifyDriverShm_sendEvent".
I already had a look at the IPC optimizing tips.
There it says that GateMP could be configured to own needs.
Actually GateMP is set as follows:
Local protection is set to "TASKLET" (I'm not using IPC from within HWIs)
Remote protection is set to "SYSTEM".
What does "SYSTEM" mean here? Is it realised with HWI protection?
If yes, can I configure "SYSTEM" protection to also only protect SWIs and tasks (like local protection)?
Besides "SYSTEM" there is a "CUSTOM1" and "CUSTOM2" remote protection. How are these used?
Any other hints / ideas?
Regards,
Markus
Hello.
I'm using TDA4VM EVM & PSDKRA / PSDKLA v0.9.
But application app_single_cam_main appRemoteServiceRun function for MCU2_1 is hanging.
application is stopped.
It looks like IPC call for MPU1_0 --> MCU2_1 is not working, so it is hanging.
For using IM_SENSOR_CMD_QUERY ... IOCTL appRemoteServiceRun have to run.
Is there any modify point for this problem at PSDKRA v0.9 ?
regards,
Jukyeong
Part Number: AM3358
Hi,
This issue is similar to the previous thread https://e2e.ti.com/support/processors/f/791/t/472060
On our circuit board, the VBUS is connected to 5V always. We tried the instruction described in the thread mentioned above, still could not make the host work----VBUS_ERROR is reported.
The SDK is 5.02. The log is listed below. Should we make additional changes? Thanks,
[ 22.939089] FAT-fs (mmcblk1p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
[ 27.969522] am335x-phy-driver 47401300.usb-phy: 47401300.usb-phy supply vcc not found, using dummy regulator
[ 28.284010] musb-hdrc musb-hdrc.0: MUSB HDRC host driver
[ 28.360761] musb-hdrc musb-hdrc.0: new USB bus registered, assigned bus number 1
[ 28.518771] hub 1-0:1.0: USB hub found
[ 28.544942] hub 1-0:1.0: 1 port detected
[ 28.583772] am335x-phy-driver 47401b00.usb-phy: 47401b00.usb-phy supply vcc not found, using dummy regulator
[ 28.663786] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
[ 28.740669] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 2
[ 28.789861] pruss 4a300000.pruss: creating PRU cores and other child platform devices
[ 28.859745] hub 2-0:1.0: USB hub found
[ 28.888777] hub 2-0:1.0: 1 port detected
[ 29.071592] remoteproc remoteproc1: 4a334000.pru is available
[ 29.120359] pru-rproc 4a334000.pru: PRU rproc node /ocp/pruss_soc_bus@4a326004/pruss@0/pru@34000 probed successfully
[ 29.177838] remoteproc remoteproc2: 4a338000.pru is available
[ 29.183803] pru-rproc 4a338000.pru: PRU rproc node /ocp/pruss_soc_bus@4a326004/pruss@0/pru@38000 probed successfully
[ 29.194511] musb-hdrc musb-hdrc.0: VBUS_ERROR in a_wait_vrise (80, <SessEnd), retry #3, port1 0008010c
Part Number: DRA77P
Tool/software: Linux
Hi,
The previous thread has not been resolved, By mistake it was attended as resolved.
On running the debug clock scipt, I get the following, provided the device tree endpoint in dss tda19988_in is commented out.
=====================DSS clock script=================== Dumps internal clocks and muxes of DSS CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002AB video1 PLL : Disabled video2 PLL : Disabled HDMI PLL : Enabled DSI1_A_CLK mux : DPLL HDMI DSI1_B_CLK mux : DPLL video2 DSI1_C_CLK mux : DPLL Video1 DSS_CTRL (0x58000040) = 0x00000000 2: LCD1 clk switch : DSS clk 3: LCD2 clk switch : DSS clk 10: LCD3 clk switch : DSS clk 1: func clk switch : DSS clk 13: DPI1 output : HDMI DSS_STATUS (0x5800005C) = 0x01408A81 DSI_CLK_CTRL (0x58004054) = 0x00000001 CM_DSS_CLKSTCTRL (0x4A009100) = 0x00040B03 CM_DSS_DSS_CLKCTRL (0x4A009120) = 0x00000702 ======================================================== Register dump for DPLL hdmi |----------------------------| | Address (hex) | Data (hex) | |----------------------------| | 0x58040200 | 0x00000018 | | 0x58040204 | 0x00000003 | | 0x58040208 | 0x00000000 | | 0x5804020C | 0x0004A40E | | 0x58040210 | 0x00602004 | | 0x58040214 | 0x00001800 | | 0x58040218 | 0x00000000 | | 0x5804021C | 0x00000000 | | 0x58040220 | 0x00080000 | |----------------------------| Details for DPLL hdmi PLL status : Locked M4 hsdiv(1) : inactive M5 hsdiv(2) : inactive M6 hsdiv(3) : inactive M7 hsdiv(4) : inactive PLL_REGM = 594 PLL_REGN = 7 M4 DIV = 0 M6 DIV = 0 M7 DIV = 0 PLL_REGM2 = 2 PLL_REGM_F = 2 PLL_SD = 6 HDMI_SSC_CONFIGURATION1(should be zero) 0x00000000 HDMI_SSC_CONFIGURATION2(should be zero) 0x00000000 Clock calculations (DPLL hdmi) sysclk = 20000000 CLKOUT = sysclk * REGM / (REGM2 * (REGN + 1)) = 742500000 ======================================================== Clock O/P of MUXes DPLL PER H12 Output 192000000 CM_DIV_H12_DPLL_PER (0x4A00815C) = 0x00000204 DSI1_A_CLK : 742500000 DSI1_B_CLK : 0 DSI1_C_CLK : 0 DISPC_DIVISOR (0x58001804) = 0x00010001 2: LCD1 clk : 192000000 3: LCD2 clk : 192000000 10: LCD3 clk : 192000000 1: func clk : 192000000 LCD1 logic clk(/ 1 ) : 192000000 pix clk(/ 2 ) : 96000000 LCD2 logic clk(/ 4 ) : 48000000 pix clk(/ 1 ) : 48000000 LCD3 logic clk(/ 4 ) : 48000000 pix clk(/ 1 ) : 4800000
When the dpi_out endpoint is made as lcd_out by giving a dummy lcd panel node, I get the following result,
=====================DSS clock script=================== Dumps internal clocks and muxes of DSS CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002A2 video1 PLL : Enabled video2 PLL : Disabled HDMI PLL : Enabled DSI1_A_CLK mux : DPLL Video1 DSI1_B_CLK mux : DPLL video2 DSI1_C_CLK mux : DPLL Video1 DSS_CTRL (0x58000040) = 0x00010001 2: LCD1 clk switch : DSI1_A_CLK 3: LCD2 clk switch : DSS clk 10: LCD3 clk switch : DSS clk 1: func clk switch : DSS clk 13: DPI1 output : LCD1 DSS_STATUS (0x5800005C) = 0x01408A82 DSI_CLK_CTRL (0x58004054) = 0x80004001 CM_DSS_CLKSTCTRL (0x4A009100) = 0x00040F03 CM_DSS_DSS_CLKCTRL (0x4A009120) = 0x00001702 ======================================================== Register dump for DPLL video1 |----------------------------| | Address (hex) | Data (hex) | |----------------------------| | 0x58004300 | 0x00000018 | | 0x58004304 | 0x00002F83 | | 0x58004308 | 0x00000000 | | 0x5800430C | 0x252AA44E | | 0x58004310 | 0x02E56008 | | 0x58004314 | 0x00000129 | | 0x58004318 | 0x00000000 | | 0x5800431C | 0x00000000 | | 0x58004320 | 0x00000000 | |----------------------------| Details for DPLL video1 PLL status : Locked M4 hsdiv(1) : Active M5 hsdiv(2) : Active M6 hsdiv(3) : Active M7 hsdiv(4) : Active PLL_REGM = 1362 PLL_REGN = 39 M4 DIV = 9 M6 DIV = 9 M7 DIV = 9 Clock calculations (DPLL video1) sysclk = 20000000 DCO clk = sysclk * 2 * REGM / (REGN + 1) = 1362000000 M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 136200000 M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 136200000 M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 136200000 ======================================================== Register dump for DPLL hdmi |----------------------------| | Address (hex) | Data (hex) | |----------------------------| | 0x58040200 | 0x00000018 | | 0x58040204 | 0x00000003 | | 0x58040208 | 0x00000000 | | 0x5804020C | 0x0004A40E | | 0x58040210 | 0x00602004 | | 0x58040214 | 0x00001800 | | 0x58040218 | 0x00000000 | | 0x5804021C | 0x00000000 | | 0x58040220 | 0x00080000 | |----------------------------| Details for DPLL hdmi PLL status : Locked M4 hsdiv(1) : inactive M5 hsdiv(2) : inactive M6 hsdiv(3) : inactive M7 hsdiv(4) : inactive PLL_REGM = 594 PLL_REGN = 7 M4 DIV = 0 M6 DIV = 0 M7 DIV = 0 PLL_REGM2 = 2 PLL_REGM_F = 2 PLL_SD = 6 HDMI_SSC_CONFIGURATION1(should be zero) 0x00000000 HDMI_SSC_CONFIGURATION2(should be zero) 0x00000000 Clock calculations (DPLL hdmi) sysclk = 20000000 CLKOUT = sysclk * REGM / (REGM2 * (REGN + 1)) = 742500000 ======================================================== Clock O/P of MUXes DPLL PER H12 Output 192000000 CM_DIV_H12_DPLL_PER (0x4A00815C) = 0x00000204 DSI1_A_CLK : 136200000 DSI1_B_CLK : 0 DSI1_C_CLK : 136200000 DISPC_DIVISOR (0x58001804) = 0x00010001 2: LCD1 clk : 136200000 3: LCD2 clk : 192000000 10: LCD3 clk : 192000000 1: func clk : 192000000 LCD1 logic clk(/ 1 ) : 136200000 pix clk(/ 3 ) : 45400000 LCD2 logic clk(/ 4 ) : 48000000 pix clk(/ 1 ) : 48000000 LCD3 logic clk(/ 4 ) : 48000000 pix clk(/ 1 ) : 48000000
When dpi_out endpoint is given to tda19988_in, nothing works and the working dedicated hdmi also fails.
Can I get a detail on where to look.
Regards,
Padmesh
Part Number: TMS320C6678
Dear everyone:
I have tested the example led_blink in ti-processor-sdk-rtos-c667x-evm-06.00.00.07 . In this example , it lets the GPIO_9 Output a high level voltage. I used a voltmeter to detect the voltage of GPIO_9 and found it to be 1.5v. But I need it to be 1.8v. I think that I should start with the GPIO pin configuration, modify it and let it output 1.8v. The follow codes is the configuration of GPIO pin.
GPIO_DEVICE_CONFIG(GPIO_LED1_PORT_NUM, GPIO_LED1_PIN_NUM) |
GPIO_CFG_OUTPUT,
The parameter GPIO_CFG_OUTPUTmay mark the properties of the pin , so which parameter represents 1.8v? Thank you for your help!
Best wishes!
Part Number: TDA2P-ACD
Hi All,
We have a plug-in in which we want to accept multiple(4) consecutive frames sent from previous link i.e VPE for processing. ( VPE -> MultiProcess (DSP1) )
We have added the below for loop changes in our plugin to accept the consecutive frames in the process function:
for(frmCount = 0; frmCount < 3; frmCount++)
{
System_getLinksFullBuffers(pMultiProcessObj->inQueParams.prevLinkId,
pMultiProcessObj->inQueParams.prevLinkQueId,
&inputBufList);
if (inputBufList.numBuf)
{
pSysBufferInput = inputBufList.buffers[bufId];
if (pSysBufferInput->bufType != SYSTEM_BUFFER_TYPE_VIDEO_FRAME)
{
bufDropFlag = TRUE;
}
else
{
bufDropFlag = FALSE;
}
pInputBuffer = (System_VideoFrameBuffer *) pSysBufferInput->payload;
/* taking a copy of input frame into pre-defined system video frame buffer */
}
else
{
bufDropFlag = FALSE;
}
inputQId = 0;
inputBufListReturn.numBuf = 1;
inputBufListReturn.buffers[0] = pSysBufferInput;
AlgorithmLink_releaseInputBuffer(
pObj, inputQId, pMultiProcessObj->inQueParams.prevLinkId,
pMultiProcessObj->inQueParams.prevLinkQueId,
&inputBufListReturn, &bufDropFlag);
}
Vps_printf("After 3 frames !!!");
After this, in the process, the 4th frame is accepted. Then we want to process these frames but We are not getting any output. Below is the performance statistics for VPE and our plugin.
[IPU1-0] 20.021533 s: [ VPE ] Link Statistics,
[IPU1-0] 20.021594 s: ******************************
[IPU1-0] 20.021808 s:
[IPU1-0] 20.021869 s: Elapsed time = 13796 msec
[IPU1-0] 20.021930 s:
[IPU1-0] 20.021991 s: New data Recv = 30.0 fps
[IPU1-0] 20.022052 s: Get Full Buf Cb = 0.21 fps
[IPU1-0] 20.022143 s: Driver/Notify Cb = 120.3 fps
[IPU1-0] 20.022204 s:
[IPU1-0] 20.022235 s: Input Statistics,
[IPU1-0] 20.022296 s:
[IPU1-0] 20.022326 s: CH | In Recv | In Drop | In User Drop | In Process
[IPU1-0] 20.022418 s: | FPS | FPS | FPS | FPS
[IPU1-0] 20.022479 s: --------------------------------------------------
[IPU1-0] 20.022570 s: 0 | 120. 3 0. 0 0. 0 0.28
[IPU1-0] 20.022692 s:
[IPU1-0] 20.022723 s: Output Statistics,
[IPU1-0] 20.022845 s:
[IPU1-0] 20.022875 s: CH | Out | Out | Out Drop | Out User Drop
[IPU1-0] 20.022967 s: | ID | FPS | FPS | FPS
[IPU1-0] 20.023028 s: ---------------------------------------------
[IPU1-0] 20.023119 s: 0 | 0 0.28 119.74 0. 0
[IPU1-0] 20.023211 s:
[IPU1-0] 20.023272 s: [ VPE ] LATENCY,
[IPU1-0] 20.023302 s: ********************
[IPU1-0] 20.023363 s: Local Link Latency : Avg = 960 us, Min = 915 us, Max = 1037 us,
[IPU1-0] 20.023485 s: Source to Link Latency : Avg = 7991 us, Min = 5643 us, Max = 10736 us,
[IPU1-0] 20.023607 s:
[IPU1-0] 20.023699 s:
[IPU1-0] 20.023760 s: ### CPU [IPU1-0], LinkID [ 1],
[IPU1-0] 20.023882 s:
[IPU1-0] 20.023912 s: [ IPC_OUT_1 ] Link Statistics,
[IPU1-0] 20.024004 s: ******************************
[IPU1-0] 20.024065 s:
[IPU1-0] 20.024095 s: Elapsed time = 13797 msec
[IPU1-0] 20.024156 s:
[IPU1-0] 20.024187 s: New data Recv = 0.21 fps
[IPU1-0] 20.024278 s: Release data Recv = 0.7 fps
[IPU1-0] 20.024339 s: Driver/Notify Cb = 33.77 fps
[IPU1-0] 20.024431 s:
[IPU1-0] 20.024461 s: Input Statistics,
[IPU1-0] 20.024522 s:
[IPU1-0] 20.024553 s: CH | In Recv | In Drop | In User Drop | In Process
[IPU1-0] 20.024614 s: | FPS | FPS | FPS | FPS
[IPU1-0] 20.024705 s: --------------------------------------------------
[IPU1-0] 20.024827 s: 0 | 0.21 0. 0 0. 0 0.21
[IPU1-0] 20.024949 s:
[IPU1-0] 20.025010 s: Output Statistics,
[IPU1-0] 20.025041 s:
[IPU1-0] 20.025102 s: CH | Out | Out | Out Drop | Out User Drop
[IPU1-0] 20.025163 s: | ID | FPS | FPS | FPS
[IPU1-0] 20.025254 s: ---------------------------------------------
[IPU1-0] 20.025315 s: 0 | 0 0.21 0. 0 0. 0
[IPU1-0] 20.025437 s:
[IPU1-0] 20.025468 s: [ IPC_OUT_1 ] LATENCY,
[IPU1-0] 20.025529 s: ********************
[IPU1-0] 20.025590 s: Local Link Latency : Avg = 10 us, Min = 0 us, Max = 30 us,
[IPU1-0] 20.025712 s: Source to Link Latency : Avg = 7300 us, Min = 5856 us, Max = 8693 us,
[IPU1-0] 20.026047 s:
[IPU1-0] 20.525895 s:
[IPU1-0] 20.525956 s: ### CPU [ DSP1], LinkID [ 11],
[IPU1-0] 20.526047 s:
[IPU1-0] 20.526169 s: [ IPC_IN_1 ] Link Statistics,
[IPU1-0] 20.526230 s: ******************************
[IPU1-0] 20.526291 s:
[IPU1-0] 20.526352 s: Elapsed time = 14299 msec
[IPU1-0] 20.526413 s:
[IPU1-0] 20.526444 s: Get Full Buf Cb = 0.55 fps
[IPU1-0] 20.526535 s: Put Empty Buf Cb = 0.41 fps
[IPU1-0] 20.526596 s: Driver/Notify Cb = 33.49 fps
[IPU1-0] 20.526688 s:
[IPU1-0] 20.526718 s: Input Statistics,
[IPU1-0] 20.526993 s:
[IPU1-0] 20.527054 s: CH | In Recv | In Drop | In User Drop | In Process
[IPU1-0] 20.527145 s: | FPS | FPS | FPS | FPS
[IPU1-0] 20.527206 s: --------------------------------------------------
[IPU1-0] 20.527298 s: 0 | 0.20 0. 0 0. 0 0.20
[IPU1-0] 20.527420 s:
[IPU1-0] 20.527450 s: Output Statistics,
[IPU1-0] 20.527511 s:
[IPU1-0] 20.527542 s: CH | Out | Out | Out Drop | Out User Drop
[IPU1-0] 20.527633 s: | ID | FPS | FPS | FPS
[IPU1-0] 20.527694 s: ---------------------------------------------
[IPU1-0] 20.527847 s: 0 | 0 0.20 0. 0 0. 0
[IPU1-0] 20.527969 s:
[IPU1-0] 20.527999 s: [ IPC_IN_1 ] LATENCY,
[IPU1-0] 20.528060 s: ********************
[IPU1-0] 20.528121 s: Local Link Latency : Avg = 10 us, Min = 0 us, Max = 30 us,
[IPU1-0] 20.528243 s: Source to Link Latency : Avg = 8560 us, Min = 5948 us, Max = 9882 us,
[IPU1-0] 20.528365 s:
[IPU1-0] 20.528457 s:
[IPU1-0] 20.528518 s: ### CPU [ DSP1], LinkID [ 49],
[IPU1-0] 20.528579 s:
[IPU1-0] 20.528609 s: [ ALG_MULTIPROCESS ] Link Statistics,
[IPU1-0] 20.528701 s: ******************************
[IPU1-0] 20.528762 s:
[IPU1-0] 20.528853 s: Elapsed time = 14462 msec
[IPU1-0] 20.528914 s:
[IPU1-0] 20.528975 s: New data Recv = 0.13 fps
[IPU1-0] 20.529036 s:
[IPU1-0] 20.529067 s: Input Statistics,
[IPU1-0] 20.529128 s:
[IPU1-0] 20.529158 s: CH | In Recv | In Drop | In User Drop | In Process
[IPU1-0] 20.529250 s: | FPS | FPS | FPS | FPS
[IPU1-0] 20.529311 s: --------------------------------------------------
[IPU1-0] 20.529402 s:
[IPU1-0] 20.529433 s: Output Statistics,
[IPU1-0] 20.529494 s:
[IPU1-0] 20.529524 s: CH | Out | Out | Out Drop | Out User Drop
[IPU1-0] 20.529616 s: | ID | FPS | FPS | FPS
[IPU1-0] 20.529677 s: ---------------------------------------------
[IPU1-0] 20.529768 s:
[IPU1-0] 20.529860 s: [ ALG_MULTIPROCESS ] LATENCY,
[IPU1-0] 20.529921 s: ********************
[IPU1-0] 20.529982 s:
[IPU1-0] 20.530073 s:
[IPU1-0] 20.530134 s: ### CPU [ DSP1], LinkID [ 1],
[IPU1-0] 20.530195 s:
[IPU1-0] 20.530226 s: [ IPC_OUT_1 ] Link Statistics,
[IPU1-0] 20.530317 s: ******************************
[IPU1-0] 20.530378 s:
[IPU1-0] 20.530409 s: Elapsed time = 14463 msec
[IPU1-0] 20.530470 s:
[IPU1-0] 20.530500 s: Driver/Notify Cb = 33.11 fps
[IPU1-0] 20.530592 s:
[IPU1-0] 20.530622 s: Input Statistics,
[IPU1-0] 20.530683 s:
[IPU1-0] 20.530714 s: CH | In Recv | In Drop | In User Drop | In Process
[IPU1-0] 20.530836 s: | FPS | FPS | FPS | FPS
[IPU1-0] 20.530927 s: --------------------------------------------------
[IPU1-0] 20.531019 s:
[IPU1-0] 20.531049 s: Output Statistics,
[IPU1-0] 20.531080 s:
[IPU1-0] 20.531141 s: CH | Out | Out | Out Drop | Out User Drop
[IPU1-0] 20.531202 s: | ID | FPS | FPS | FPS
[IPU1-0] 20.531293 s: ---------------------------------------------
[IPU1-0] 20.531354 s:
Could you please let us know if we have correctly accepted the 4 frames ? And what could be the issue for no output to further links ?
Regards,
Amol
Part Number: TMS320C6678
Hi,
mcsdk_2_01_02_06
ndk_2_21_02_43
ipc_1_24_03_32
The customer ping core0 from PC and Core0, Core1, Core 2 send messages to each other by MessageQ.
When using messageQ, ping will have a delay of tens of ms, if not,the delay within 1ms.
What may cause that? Any suggestions to optimize the procedure?
Part Number: 66AK2G12
Hi ,
In our audio setup, we have three inputs, one DIR and two ADC. And when we try to switch between the inputs, some times the mcasp receiver side state machine is not coming out of reset within timeout. This I observed by looking the GBLCTL registers during a successful transition. During a successful input transition, I could see that the RFRST and RSMRST bits gets reset and immediately comes back to set state and so the operation proceeds without any issue. But in an unsuccessful transition, the state machine doesn't come out of reset, within timeout and it leads to an abort.
Here the main issue is that, the values are not getting written to RGBLCTL even though we are using the write API to write into that. And in the loop for reading back the value from GBLCTL, it goes into timeout and then aborts.
We are re-initializing the mcasp during each input switch.
Along with this, I have some questions, which is mentioned below.
Part Number: AM4377
The AM4377 uses the RMII interface to connect to the DP83848 and connects to the computer via a network cable (the network card is the Intel(R) PRO/1000 MT Dual Port Server Adapter).
Uboot network port is not available, please help us to see if the hardware pin connection and pinmux configuration is normal? Thank you!
Schematic reference annex:(Please visit the site to view this file)
Serial port printing reference attachment:（uboot use ti-processor-sdk-linux-am437x-evm-03.02.00.05-Linux-x86-Install.bin）
(Please visit the site to view this file)
Pinmux settings:
static struct module_pin_mux rmii2_pin_mux[] = {
{OFFSET(gpmc_a0), MODE(3)| SLEWCTRL}, /* RMII2_TXEN：*/
{OFFSET(gpmc_a4), MODE(3)| SLEWCTRL}, /* RMII2_TXD1：*/
{OFFSET(gpmc_a5), MODE(3)| SLEWCTRL}, /* RMII2_TXD0：*/
{OFFSET(gpmc_a10), MODE(3) | SLEWCTRL | RXACTIVE}, /* RMII2_RXD1：*/
{OFFSET(gpmc_a11), MODE(3) | SLEWCTRL | RXACTIVE}, /* RMII2_RXD0：*/
{OFFSET(gpmc_wait0), MODE(3) | PULLUP_EN | RXACTIVE}, /* RMII2_CRS_DV：*/
{OFFSET(gpmc_wpn), MODE(3) | SLEWCTRL | RXACTIVE}, /* RMII2_RXER：*/
{OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* RMII2_refclk：*/
{-1},
};
other setting：
1）auto negotiation enabled on both ends of the link，The PC's Network card has also been set to auto-negotiation mode.
2）the link speeds is 100 Mbps.The PC's Network card rate query is also 100M.
3）Full Duplex mode is correct.
CRSC># mdio read 0-7 （----when uboot）
Reading from bus cpsw
PHY at address 1:
0 - 0x3100 --ok
1 - 0x786d
2 - 0x2000
3 - 0x5c90
4 - 0x1e1
5 - 0xc1e1 --1 = Link Partner desires Next Page Transfer.
6 - 0xf --1 = Link Partner does support Next Page
7 - 0x2801
CRSC># md 4a100900
4a100900: 00000000 00000000 00000000 00000000 ................
4a100910: 00000000 00000000 00000000 00000000 ................
4a100920: 00000000 00000000 00000000 00000000 ................
4a100930: 00000000 00000000 00000000 00000000 ................
4a100940: 00000000 00000000 00000000 00000000 ................
4a100950: 00000000 00000000 00000000 00000000 ................
4a100960: 00000000 00000000 00000000 00000000 ................
4a100970: 00000000 00000000 00000000 00000000 ................
4a100980: 00000000 00000000 00000000 00000000 ................
uboot code modified：(Please visit the site to view this file)(Please visit the site to view this file)(Please visit the site to view this file)
thank you！
Part Number: AM3352
Dear Champs,
My customer find the high-byte DQS(UDQS) signal was sent before low-byte DQS(LDQS) and thus there was data missing occurred in high-byte.
Is there any way to control UDQS output time to same as LDQS output time?
My customer changed DDR3 memory in their board and found booting fail occurred.
When I checked their board, I found data missing in the high-byte of memory window in the ccs.
The below is my customer's analysis, and they are afraid that there are too many gaps between UDQS time and LDQS time.
* TI AM3352 sends high-byte DQS (UDQS) before low-byte (LDQS) as waveforms check with UDQS and LDQS,
* But WRITE DQS check with M15F1G1664A(2CS), it seems no consecutive DQS running on AM3352, that means booting failed.
* We suppose that data will be missed to strobe during WRITE cycle, if skew is too wide between UDQS and LDQS sent by chipset.
the below is the measurement data. blue line is UDQS and green line is LDQS.
you can find Time gap of 219.26ps at Rising time and 194.14ps at Falling time.
Read tCK(avg): 2.5 ~ 3.3ns, CL=6tCK, Write CWL = 5tCK.
So, if there is a way to control UDQS output time, it would be very helpful.
Thanks and Best Regards,
SI.
