AM5708: PTP peer delay issue

August 9, 2019, 12:40 am

≫ Next: DRA829 jtag working when main domain down ?

≪ Previous: TMDSCSK8127: TMDSCSK8127

Part Number: AM5708

I have a custom AM5708 based board.I am running "ptp4l" acting as a slave only device. The issue is as follows:

If the master does not provide p2p delay response, the board does not synchronize.

I was trying to find any parameter or configuration value that could deal with this issue and also tried

to find a response in the web but found nothing.

Do you know if ptp4l stack needs p2p mechanism to synchronize the bridge clock? I think that

the fact that the master does not provide p2p response should not keep the slave from synchronizing.

Regards

Billa

↧

DRA829 jtag working when main domain down ?

August 9, 2019, 12:44 am

≫ Next: AM5708: PTP offset

≪ Previous: AM5708: PTP peer delay issue

Hi everybody ,

I can see only 1 jtag connector in schematics .

now I need to work on mcu island and debugging even if main domain power is down : does Jtag works even if main domain power is off ?

should I have any HW trick to allow that ?

regards

Carlo

↧

AM5708: PTP offset

August 9, 2019, 12:44 am

≫ Next: CCS/TDA3MV: Possibility evaluation of TDA3x plus 2MP Surround view cameras

≪ Previous: DRA829 jtag working when main domain down ?

Part Number: AM5708

I have a custom AM5708 based board.I am running "ptp4l" acting as a slave only device. The issue is as follows:

I have two PTP master clocks: one from GE and another from MEINBERG.

If I connect the MEINBERG master clock to the slave board, this synchronizes fine.

If then I disconnect the MEINMBERG master clock and connect the GE master clock to the slave board, this synchronizes fine.

If then I disconnect the GE master clock and connect the MEINBERG master clock to the slave board, this time the slave board

synchronizes but with and offset of 25 msec with respect to the master.

If then I disconnect the MEINMBERG master clock and connect the GE master clock to the slave board, this synchronizes fine.

From this moment on, every time that I try to synchronize with the MEINBERG master clock I get the 25 msec offset.

To return to the original situation I have to reboot the bridge.

Regards

Billa

↧

CCS/TDA3MV: Possibility evaluation of TDA3x plus 2MP Surround view cameras

August 9, 2019, 12:45 am

≫ Next: dra829 ethernet in mcu island used by multiprocessor at same time

≪ Previous: AM5708: PTP offset

Part Number: TDA3MV

Tool/software: Code Composer Studio

TDA3X supports 1Mega surround view cameras at default condition for TDA3X EVM, please evaluate possibility of TDA3x plus 2MP Surround view cameras ?

1. GPU: As we know, TDA3x does not include GPU module, TDA3X implement 3D with ARM core or DSP core; Does TDA3X computing force support 2Mega 3D surround view cameras?

2. Interface : 2 * MIPI

3. SerDes:

4. Integrated ISP: what kinds of CMOS sensors does internal ISP of TDA3x ?

↧

dra829 ethernet in mcu island used by multiprocessor at same time

August 9, 2019, 12:56 am

≫ Next: AM5706: Power consumption summary

≪ Previous: CCS/TDA3MV: Possibility evaluation of TDA3x plus 2MP Surround view cameras

Hi everybody ,

I need to use Ethernet on MCU side for safety concern . Now R5 will do booting etc and early services but when main domain is on I would like some services ( like web server ) handled by main domain , and at the same time R5 in the MCU island serving other services ( like UDP, ping etc ) .

is it possible ? should I use some IPC level on R5 to talk to main island processors ? any usggestion /example ?

best regards

Carlo

↧

AM5706: Power consumption summary

August 9, 2019, 1:03 am

≫ Next: TDA2EVM5777: How to set SEL_ENET_MUX_S0 output low level

≪ Previous: dra829 ethernet in mcu island used by multiprocessor at same time

Part Number: AM5706

Is there a detailed description of the current consumption of each power supply of AM5706 like the AM3354?

↧

TDA2EVM5777: How to set SEL_ENET_MUX_S0 output low level

August 9, 2019, 1:57 am

≫ Next: EVMK2H: XDS2xx MIPI board 14 Pin connector (J5).

≪ Previous: AM5706: Power consumption summary

Part Number: TDA2EVM5777

Hi,

1、How to set SEL_ENET_MUX_S0 output low level.let A1 port = B2 port.whether it is set like this

&ovcam5 {
mux-gpios =
<&pcf_gpio_21 4 GPIO_ACTIVE_LOW>; /* SEL_ENET_MUX_S0 */
};(dra7-evm-vision.dts : ti_components/os_tools/linux/kernel/omap/arch/arm/boot/dts/)

but I set the test SEL_ENET_MUX_S0 terminal voltage to 3.3V.

↧

EVMK2H: XDS2xx MIPI board 14 Pin connector (J5).

August 9, 2019, 2:01 am

≫ Next: EVMK2H: Using an external JTAG

≪ Previous: TDA2EVM5777: How to set SEL_ENET_MUX_S0 output low level

Part Number: EVMK2H

Hi,

We have a EVMK2H Evaluation Module with us and we are trying to figure how we can connect to external JTAG Emulator. The Evaluation module has a XDS2xx MIPI board also. The board has one MIPI 60 connector for interfacing external JTAG emulator and also there is a 14 pin connector (J5) which is not assembled. We would like to know whether this connector can be used to connect an external JTAG emulator via Ti 14 pin interface.

With Regards

↧

EVMK2H: Using an external JTAG

August 9, 2019, 2:20 am

≫ Next: AM5728: LTP-DDT problem

≪ Previous: EVMK2H: XDS2xx MIPI board 14 Pin connector (J5).

Part Number: EVMK2H

Hi,

My customer is using EVMK2H.
He wants to remove XDS200 card connected on EVMK2H as the card conflicts with a component he wants to connect with EVM.

So he needs to use an external JTAG cable for debug.
In this case, an external JTAG’s MIPI-60 header can be directly connected to EMU1 on EVM, correct?

Thanks and regards,
Koichiro Tashiro

↧

AM5728: LTP-DDT problem

August 9, 2019, 4:07 am

≫ Next: CCS/TMS320C6748: Any code example?

≪ Previous: EVMK2H: Using an external JTAG

Part Number: AM5728

I copy the paltform file am57xx-evm to am57xx-myboard and change it ike following:

armv7l
dra7xx
am57xx-myboard

but there is so many errors:

<<<test_start>>>
tag=VIDEO_S_FUNC_GST_MPEG4_480P stime=1562477083
cmdline="source 'common.sh'; do_cmd 'gst.sh -d "M4V/HistoryOfTI-480p.m4v" -c "mpeg4" -r "480p"'"
contacts=""
analysis=exit
<<<test_output>>>
|TRACE LOG|Inside do_cmd:CMD=gst.sh -d "M4V/HistoryOfTI-480p.m4v" -c "mpeg4" -r "480p"|
Demo file /usr/share/ti/video/HistoryOfTI-480p.m4v exists
|TRACE LOG|Inside do_cmd:CMD=gst-launch-1.0 playbin uri=file:///usr/share/ti/video/HistoryOfTI-480p.m4v video-sink="kmssink" audio-sink="alsasink"|
Setting pipeline to PAUSED ...
ERROR: Pipeline doesn't want to pause.
ERROR: from element /GstAlsaSink:alsasink0: Could not open audio device for playback.
Additional debug info:
../../../gst-plugins-base-1.14.4/ext/alsa/gstalsasink.c(865): gst_alsasink_open (): /GstAlsaSink:alsasink0:
Playback open error on device 'default': No such file or directory
Setting pipeline to NULL ...
Freeing pipeline ...
|ERROR|Line: File:gst-launch-1.0 playbin uri=file:///usr/share/ti/video/HistoryOfTI-480p.m4v video-sink="kmssink" audio-sink="alsasink" failed. Return code is 255 - |
|ERROR|Line: File:gst.sh -d "M4V/HistoryOfTI-480p.m4v" -c "mpeg4" -r "480p" failed. Return code is 255 - |
<<<execution_status>>>
initiation_status="ok"
duration=0 termination_type=exited termination_id=255 corefile=no
cutime=12 cstime=2
<<<test_end>>>

So, what'this? How does the runltp use the platform file to decide the test?

↧

CCS/TMS320C6748: Any code example?

August 9, 2019, 4:19 am

≫ Next: AM5718: USB2 VBUS detect

≪ Previous: AM5728: LTP-DDT problem

Part Number: TMS320C6748

Tool/software: Code Composer Studio

Could someone show me how to find code example to play with TMS320C6748EZ starter kit, like FLASH, USB, DRAM, BOOTLOADER? Is there a code base that I can search? Thanks!

↧

AM5718: USB2 VBUS detect

August 9, 2019, 5:16 am

≫ Next: AM3358: PRU ADC with FFTW integration

≪ Previous: CCS/TMS320C6748: Any code example?

Part Number: AM5718

Hi,

I am using AM5718 on my custom board with USB2 port used as in IDK.

The VBUS detect on IDK is connected to ball B27 (GPIO 7 22).

In my custom board VBUS detect connected to a different Ball A9 (GPIO 8 22)

As i understand in Linux

/arch/arm/boot/dts/am571x-idk.dts

&extcon_usb2 {
id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>;
};

if I modify

&gpio7 22 GPIO_ACTIVE_HIGH>

<&gpio8 21 GPIO_ACTIVE_HIGH>

The USB2 to can be ported on to my custom board. Please let us know if any other changes needed

↧

AM3358: PRU ADC with FFTW integration

August 9, 2019, 6:12 am

≫ Next: 66AK2H14: Bring up Hyperlink on custom board

≪ Previous: AM5718: USB2 VBUS detect

Part Number: AM3358

Hello,

I wrote the ADC/DMA code for a ping pong buffer configuration. The code works and it can run in the firmware correctly on the PRU. I am using the Linux SDK 06.00.00.07.

I am trying to figure out how I can integrate the ADC/DMA firmware code with FFTW. Ideally, I want to be able to do FFT calculations on the ping/pong buffers.

The issue I am having is I don't know how to integrate these two code files together. I can enable the ADC/DMA code from the FFTW code using Remoteproc. However, the issue is that since I am assuming I have to run the FFTW code in the userspace, I am not sure how to access the ping/pong buffers.

For instance, let's say my ping buffer is at 0x81000000 and my pong buffer is at 0x82000000. How can I access these buffers from the userspace in the FFTW code? I assuming all code compiled in the userspace is using virtual memory from what I understand.

Any advice is greatly appreciated.

Best Regards,

Tyler

↧

66AK2H14: Bring up Hyperlink on custom board

August 9, 2019, 7:20 am

≫ Next: AM5728: Is there any documentation or example code for setting an individual graphics pixel?

≪ Previous: AM3358: PRU ADC with FFTW integration

Part Number: 66AK2H14

Hy TI Support Team,

We are working on a custom board, which has three 66AK2H14 DSP chips. We try to communicate over Hyperlink among the DSPs. We use arago linux distro from MCSDK. I am working on the Hyperlink bring up between DSP0 and DSP1. The DSP0 HP1 port is connected to DSP1 HP0 port. I compiled a Hyperlink test program, which is obtained from the pdk_keystone2_3_01_04_07 package. This program is configured as follows by the hyplnkLLDCfg.h file:

#define hyplnk_EXAMPLE_REFCLK_156p25

#define hyplnk_EXAMPLE_ALLOW_4_LANES

#define hyplnk_EXAMPLE_SERRATE_03p125

#define hyplnk_EXAMPLE_ASYNC_CLOCKS

First the program runs in loopback mode. On the DSP0 chip the program successfully finishes the test. The DSP1 chip exits with lError and rError.

After this test, I ran the program in non-loopback mode. I managed to communicate between the chips: The program outputs are the following:

# DSP0 log:

Version #: 0x02010008; string HYPLNK LLD Revision: 02.01.00.08:Aug 5 2019:10:04:37
About to do system setup (PLL, PSC, and DDR)
Power domain is already enabled. You probably re-ran without device reset (which is OK)
Constructed SERDES configs: PLL=0x00000250; RX=0x0046c495; TX=0x000ccf95
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 1
========================================== begin registers before initialization ===========
Revision register contents:
Raw    = 0x4e902101
Scheme = 1
BU     = 0
Func   = 0x0e90
RTL    = 4
cust   = 0
revMaj = 1
revMin = 1
Status register contents:
Raw        = 0x00002004
swidthin   = 0
swidthout = 0
serialHalt = 1
pllUnlock = 0
rPend      = 0
iFlow      = 0
oFlow      = 0
rError     = 0
lError     = 0
nfEmpty3   = 0
nfEmpty2   = 0
nfEmpty1   = 0
nfEmpty0   = 0
sPend      = 1
mPend      = 0
link       = 0
Link status register contents:
Raw       = 0x00000000
txPlsReq = 0
txPlsAck = 0
txPmReq   = 0
txRSync   = 0
txPlsOK   = 0
txPhyEn   = 0
txFlowSts = 0
rxPlsReq = 0
rxPlsAck = 0
rxPmReq   = 0
rxLSync   = 0
rxPhyEn   = 0
rxPhyPol = 0
Control register contents:
Raw             = 0x00000001
intLocal        = 0
statusIntEnable = 0
statusIntVec    = 0
int2cfg         = 0
serialStop      = 0
iLoop           = 0
reset           = 1
Control register contents:
Raw        = 0x00000000
sglErrCor = 0
dblErrDet = 0
============== end registers before initialization ===========
Hyperlink Serdes Common Init Complete
Hyperlink Serdes Lane 0 Init Complete
Hyperlink Serdes Lane 1 Init Complete
Hyperlink Serdes Lane 2 Init Complete
Hyperlink Serdes Lane 3 Init Complete
[ INFO ] Hyperlink Example default SERDES setup done.
[ INFO ] Take out of reset loopback
[ INFO ] Don't care about rev reg any more
[ INFO ] Wait for peripheral to come up                            <--- the program waits here for the other side to start, At this time I start the test program on DSP1
============== begin registers after initialization ===========
Status register contents:
Raw        = 0x04402005
swidthin   = 4
swidthout = 4
serialHalt = 1
pllUnlock = 0
rPend      = 0
iFlow      = 0
oFlow      = 0
rError     = 0
lError     = 0
nfEmpty3   = 0
nfEmpty2   = 0
nfEmpty1   = 0
nfEmpty0   = 0
sPend      = 1
mPend      = 0
link       = 1
Link status register contents:
Raw       = 0xccf00cf0
txPlsReq = 3
txPlsAck = 0
txPmReq   = 3
txRSync   = 0
txPlsOK   = 0
txPhyEn   = 15
txFlowSts = 0
rxPlsReq = 0
rxPlsAck = 0
rxPmReq   = 3
rxLSync   = 0
rxPhyEn   = 15
rxPhyPol = 0
Control register contents:
Raw             = 0x00006004
intLocal        = 1
statusIntEnable = 1
statusIntVec    = 0
int2cfg         = 0
serialStop      = 1
iLoop           = 0
reset           = 0
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
Link seems stabl<-- The DSP0 freezes and must restart

## DSP1 log:

Version #: 0x02010008; string HYPLNK LLD Revision: 02.01.00.08:Sep 1 2019:02:30:48
About to do system setup (PLL, PSC, and DDR)
Power domain is already enabled. You probably re-ran without device reset (which is OK)
Constructed SERDES configs: PLL=0x00000250; RX=0x0046c495; TX=0x000ccf95
system setup worked
About to set up HyperLink Peripheral
============================Hyperlink Testing Port 0
========================================== begin registers before initialization ===========
Revision register contents:
Raw    = 0x4e902101
Scheme = 1
BU     = 0
Func   = 0x0e90
RTL    = 4
cust   = 0
revMaj = 1
revMin = 1
Status register contents:
Raw        = 0x04402197
swidthin   = 4
swidthout = 4
serialHalt = 1
pllUnlock = 0
rPend      = 0
iFlow      = 0
oFlow      = 0
rError     = 1
lError     = 1
nfEmpty3   = 0
nfEmpty2   = 0
nfEmpty1   = 1
nfEmpty0   = 0
sPend      = 1
mPend      = 1
link       = 1
Link status register contents:
Raw       = 0xfdf0bdf0
txPlsReq = 3
txPlsAck = 3
txPmReq   = 3
txRSync   = 0
txPlsOK   = 1
txPhyEn   = 15
txFlowSts = 0
rxPlsReq = 2
rxPlsAck = 3
rxPmReq   = 3
rxLSync   = 0
rxPhyEn   = 15
rxPhyPol = 0
Control register contents:
Raw             = 0x00006006
intLocal        = 1
statusIntEnable = 1
statusIntVec    = 0
int2cfg         = 0
serialStop      = 1
iLoop           = 1
reset           = 0
Control register contents:
Raw        = 0xafd10001
sglErrCor = 45009
dblErrDet = 1
============== end registers before initialization ===========
Hyperlink Serdes Common Init Complete
Hyperlink Serdes Lane 0 Init Complete
Hyperlink Serdes Lane 1 Init Complete
Hyperlink Serdes Lane 2 Init Complete
Hyperlink Serdes Lane 3 Init Complete
[ INFO ] Hyperlink Example default SERDES setup done.
[ INFO ] Take out of reset loopback
[ INFO ] Don't care about rev reg any more
[ INFO ] Wait for peripheral to come up
============== begin registers after initialization ===========
Status register contents:
Raw        = 0x04402017
swidthin   = 4
swidthout = 4
serialHalt = 1
pllUnlock = 0
rPend      = 0
iFlow      = 0
oFlow      = 0
rError     = 0
lError     = 0
nfEmpty3   = 0
nfEmpty2   = 0
nfEmpty1   = 1
nfEmpty0   = 0
sPend      = 1
mPend      = 1
link       = 1
Link status register contents:
Raw       = 0xccf00cf0
txPlsReq = 3
txPlsAck = 0
txPmReq   = 3
txRSync   = 0
txPlsOK   = 0
txPhyEn   = 15
txFlowSts = 0
rxPlsReq = 0
rxPlsAck = 0
rxPmReq   = 3
rxLSync   = 0
rxPhyEn   = 15
rxPhyPol = 0
Control register contents:
Raw             = 0x00006004
intLocal        = 1
statusIntEnable = 1
statusIntVec    = 0
int2cfg         = 0
serialStop      = 1
iLoop           = 0
reset           = 0
============== end registers after initialization ===========
Waiting 5 seconds to check link stability
Link seems stabl <-- The DSP1 freezes and must restart

Do you have any idea, what can be the problem here?

Do you think, I need a successful loopback test on DSP1 before testing it with the other chip?

Do you have any other tools to test the Hyperlink on custom devices?

Do I ran these test scripts correctly?

Do you have any idea whats next? I got stuck.

Thanks

David

↧

AM5728: Is there any documentation or example code for setting an individual graphics pixel?

August 9, 2019, 7:51 am

≫ Next: AM5728: QT and gstreamer

≪ Previous: 66AK2H14: Bring up Hyperlink on custom board

Part Number: AM5728

Hello,

I've gotten the vps dss example displayDssBareMetal running on an IDK EVM. That example displays video frames, but I need to display basic graphics. I don't see any graphics primitives in the VPS / DSS libraries. I need something similar to "set pixel".

Using the displayDssBareMetal example, I can display a video frame. I can then access memory using the frame buffer (DISPC_GFX_BA_x) but the results are inconsistent at best. The graphic format is set to 24 bit color in 32 bits (DISPC_GFX_ATTRIBUTES format xRGB24-8888) This should mean every pixel uses a "uint32". I do see an xRGB format for pixels, but writing memory to set pixels doesn't always work. I'm trying simple horizontal lines (pixels are adjacent in memory) but the pixels appear to be interlaced. I've also tried vertical lines (pixels are apart by 1920 uint32) but the pixels aren't displayed.

With a kernel running, I can access that frame buffer and it works as expected. Pixels and be changes reliably. It doesn't work with just displayDssBareMetal. I've even tried copying the values from (almost) all of the DISPC registers (0x58001000...0x58001870) from the kernel values to the displayDssBareMetal environment. It doesn't work any better.

I've reviewed the TRM many times and there is no complete graphics initialization sequence, just multiple fragments and hints. (I'm using the displayDssBareMetal example to derive the register initialization sequence)

Are there any other documentation or code examples available for graphics initialization or "get or set pixel"?

Thanks,

Scott

↧

AM5728: QT and gstreamer

August 9, 2019, 9:28 am

≫ Next: AM6526: TI-RTOS Questions

≪ Previous: AM5728: Is there any documentation or example code for setting an individual graphics pixel?

Part Number: AM5728

We are using the QT and gstreamer to playback 4 videos, do you have possible demos on this? I am interested in the demos on gstreamer, and QT.

↧

AM6526: TI-RTOS Questions

August 9, 2019, 2:11 pm

≫ Next: TCI6638K2K: Looking for the data sheet of other variety of this device; TCI6614 and TCI6630

≪ Previous: AM5728: QT and gstreamer

Part Number: AM6526

Hello,

I am working with a customer who has the following questions about the AM6526.

1) Can TI-RTOS support SMP mode on the two Cortex-A53s? I am currently using eCosPRO which supports SMP on Xilinx UltraScale. I would like TI-RTOS to do the same.

2) Can TI-RTOS be configure to have tasks as a default to run only on Cortex-A53 CPU0 and specific tasks assigned to run on the other remaining Cortex-A53 CPUx. I can do this on eCosPro.

3) Are drivers for the following peripherals available in the SDK for this SOC?

Ethernet
MCAN
MMCSD
USB
OSPI
DMA
RTI

4) Can Ti-RTOS support SMP on the two Cortex-R5Fs? I would only use them for interfacing to the Ethernet, CAN and Flash. I would not assign tasks to a particular CPU but let tasks run on both CPUs based on priority.

5) What is already in SDK for supporting Cortex-R5Fs and the Ethernet, CAN and Flash?

6) I am planning to have Cortex-A53 CPU0 to work with the Cortex-R5Fs to interface with Ethernet, CAN and Flash. I assume SDK will examples on how to do this?

7) Does TI-RTOS supports the following features? These are all supported by eCos.

OPENSSL
USTL
POSIX
NET SNTP
NS_DNTP
PPP

8) How difficult to bring up a simple system based on the above items?

Thank you for your help.

↧

TCI6638K2K: Looking for the data sheet of other variety of this device; TCI6614 and TCI6630

August 9, 2019, 3:31 pm

≫ Next: BEAGLEBK: SSH over USB

≪ Previous: AM6526: TI-RTOS Questions

Part Number: TCI6638K2K

Hi Team,

I am posting this inquiry on behalf of our customer.

The customer is originally looking for the data sheets and replacements of TCI6614, TCI6630 and TCI6638 if this parts are considered obsolete.
The TCI6638 is still in the website but in NRND status but with corresponding replacement.
But for TCI6614 and TCI6630, we don''t find any information.
Can anyone still have data sheet for TCI6614 and TCI6630? And possible replacement for this devices since we cannot find any information for this devices.

Thanks!

Jonathan

↧

BEAGLEBK: SSH over USB

August 10, 2019, 6:14 am

≫ Next: AM5728: PCIe Compliance Testing

≪ Previous: TCI6638K2K: Looking for the data sheet of other variety of this device; TCI6614 and TCI6630

Part Number: BEAGLEBK

I want to ssh into Beaglebone black from usb interface. I was successful in doing so at the first attempt. But as I rebooted the system, I am not able to do it as I don't see any ip address assigned to usb interface on host side.

Here are the system details:

Remote Side:

Beaglebone Black

OS: 4.1.15-ti-rt-r43

root@beaglebone:~# ifconfig
eth0 Link encap:Ethernet HWaddr 40:bd:32:c6:17:fd
inet addr:169.254.101.115 Bcast:169.254.255.255 Mask:255.255.0.0
inet6 addr: fe80::42bd:32ff:fec6:17fd/64 Scope:Link
UP BROADCAST RUNNING MULTICAST DYNAMIC MTU:1500 Metric:1
RX packets:1534 errors:0 dropped:0 overruns:0 frame:0
TX packets:667 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:134338 (131.1 KiB) TX bytes:376828 (367.9 KiB)
Interrupt:177

usb0 Link encap:Ethernet HWaddr 40:bd:32:c6:17:f0
inet addr:192.168.7.2 Bcast:192.168.7.3 Mask:255.255.255.252
inet6 addr: fe80::42bd:32ff:fec6:17f0/64 Scope:Link
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:1 errors:0 dropped:0 overruns:0 frame:0
TX packets:45 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:96 (96.0 B) TX bytes:13265 (12.9 KiB)

Host Side:

OS version: 5.2.6

ifconfig:

eno1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet 169.254.213.10 netmask 255.255.255.0 broadcast 169.254.213.255
inet6 fe80::4d3e:78d4:8d71:bb6c prefixlen 64 scopeid 0x20<link>
ether d4:be:d9:0b:2a:a9 txqueuelen 1000 (Ethernet)
RX packets 656 bytes 381570 (381.5 KB)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 2244 bytes 279730 (279.7 KB)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
device interrupt 20 memory 0xe2e00000-e2e20000

enx40bd32c617ff: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500
inet6 fe80::8a77:29d3:68c0:87e prefixlen 64 scopeid 0x20<link>
ether 40:bd:32:c6:17:ff txqueuelen 1000 (Ethernet)
RX packets 45 bytes 10655 (10.6 KB)
RX errors 3 dropped 0 overruns 0 frame 3
TX packets 2 bytes 540 (540.0 B)
TX errors 2668 dropped 0 overruns 0 carrier 0 collisions 0

The interface enx40bd32c617ff corresponds to usb interface (checked but I am not sure why it is not usb0). As I can see, there is no ip address assigned to it.

I tried to assign a static ip(192.168.7.1) to the interface but when I try to ssh to beaglebone black, I get the error:

ssh root@192.168.7.2
ssh: connect to host 192.168.7.2 port 22: No route to host

It would be great if someone can help me in debugging this issue.

Regards

Vishav

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AM5728: PCIe Compliance Testing

August 10, 2019, 3:37 pm

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Part Number: AM5728

Customer looking for direction/test code for PCIe GEN1 and GEN2 compliance testing and Signal Integrity measurement and testing. Any recommendation?

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