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TDA2PHV-ACD: AVS Implementation with external MCU

August 1, 2019, 10:53 pm
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Part Number: TDA2PHV-ACD

Dear, 

 

Currently we are working with the TDA2P with a PMIC without OTP, this means that we are using a external MCU to program the PMIC in order to get the proper voltages at the beginning of TDA initialization. The TDA2P is not connected to this PMIC so is not possible to establish the AVS configuration. 

 

My question is the next one, it is possible to read the voltage values which are in the TDA registers, send this values to the MCU over SPI and setting the correct voltages values after TDA initialization? Because as far as I understand, I can imagine that is not possible to read this values when the TDA is booting as the TDA do when is connected to the PMIC directly. 

 

And the second question, has sense to implement a run-time AVS, I mean, continuously connection between the TDA and MCU, to send the voltage values in runtime and adjust this values in real time?

 

Thanks and best regards. 

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WEBENCH® Tools: AM5708 BSDL file

August 1, 2019, 2:45 pm
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Tool/software: WEBENCH® Design Tools

Hello All,

I need the BSDL file for AM5708 BCBDJ  part.

Is the AM570xBABC  BSDL  (SR2_1)  working the same on my IC  AM5708 BCBDJ?

Thanks for your help,

Peter.

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TMS320DM6437Q: Solutions to TMS320DM6437Q

August 1, 2019, 10:49 pm
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Part Number: TMS320DM6437Q

Hi Expert:

can you check TMS320DM6437Q support following diagram:

1.digital video port is traditional CMOS sensor output:PCLK,HSYNC,YSYNC,DATD[0:7] or DATA[0:15]

2.RGB666 is standard RGB output

do you have the similar example or design to show it to me?

thanks.

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DRA744: [PATCH 2/4] arm: mach-omap2: Remove edma related nodes from hwmod init sequence

August 1, 2019, 11:34 pm
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Part Number: DRA744

we have enabled early late attach feature. Included below changes as part of this

 

Subject: [PATCH 2/4] arm: mach-omap2: Remove edma related nodes from hwmod

init sequence

 

When doing late attach, kernel should not reset EDMA

EDMA is setup by M4 and thus omap_hwmod needn't perform reset/setup.

Nodes 'dra7xx_l3_main_1__tpcc', 'dra7xx_l3_main_1__tptc0' and

'dra7xx_l3_main_1__tptc1' are thus disabled.

 

Note that this breaks kernel boot if not late attached.

 

Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>

---

arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 3 ---

1 file changed, 3 deletions(-)

 

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c

index 26fcb1e..ff11cb2 100644

--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c

+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c

@@ -4637,9 +4637,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {

    &dra7xx_l4_per2__mcasp8,

    &dra7xx_gmac__mdio,

    &dra7xx_l4_cfg__dma_system,

-   &dra7xx_l3_main_1__tpcc,

-   &dra7xx_l3_main_1__tptc0,

-   &dra7xx_l3_main_1__tptc1,

 

 

 

With the changes early boot is working fine, but we are missing pcm nodes and observed DMA failure.

 

[    4.332845] davinci-mcasp 48464000.mcasp: Can't verify DMA configuration (-19)

[    4.332863] davinci-mcasp 48464000.mcasp: No DMA controller found (-19)

 

Suspecting above changes.

 

In our use case we are early loading M4 - IPU1 only and IPU2 will be loaded by linux.

So we would like to know which EDMA channel needs to be late attached in our case for early loading of IPU1 alone.

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PROCESSOR-SDK-TDAX: [TIDL / DL-NAPS] I couldn't get simulation information with released DL-NAPS(00.09.00)

August 1, 2019, 11:44 pm
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Part Number: PROCESSOR-SDK-TDAX


Hello.

DL-NAPS(00.09.00) is asserted when I try to run it with my company's trained network.

It looks memory requirement is problem.
I can't find out available memory size for this problem.

--- error ---
Error: Instance memory requirement is lasrger than available memory
Couldn't allocate
ti_cnnperfsim.out: src/netmemmanger.c:645: int32_t assignMemChunk(sMemChunk*, int32_t, int32_t, sBufProperty_t*, int32_t, sConstraintDataBase_t*): Assertion `0' failed.
Aborted (core dumped)

Regards.
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AM3358: GP EVM non-TI components

August 1, 2019, 11:47 pm
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Part Number: AM3358

Hi,

My customer is using the GPEVM for their new design, but I found there are some non-TI parts on it, Ethernet PHY and USB-UART.

I'd like to recommend the TI solution, so could you please let me know alternative TI parts and TI value proposition?

1. AR8031

2. FT2232HL

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TDA2PXEVM: RTOS: Camera driver not working with LI's IMX390 FPDIII module

August 2, 2019, 12:22 am
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Part Number: TDA2PXEVM

Hello,

I am trying to bring-up LI IMX390 FPDIII camera module (Bayer sensor) on TDA2PX-EVM with PSDK version 3.7. I observed issue related to Seralizer probing.
For integration of the LI Camera module , I am using existing IMX390 sensor driver source code with same serializer (UB953) and modifying the slave address in 7-bit addressing mode of Ser (0x18) and sensor module(0x21).


Below is code snippet for our changes in source file (iss_sensor_imx390.c) in register array (gUB960DesCfg_D3IMX390[]) to program the Des(UB960) for Camera port 0, so that Serializer can be configured.

-----------------------
{0x58, 0x5E, 0x10},
{0x5B, (0x18 << 1), 0x10},
{0x5C, (0x18 << 1), 0x10},
{0x5D, 0x30, 0x10}, /*Serializer I2C Address*/
{0x5E, 0x42, 0x10}, /*Sensor I2C Address*/
{0x65, (PORT_0_SER_ADDR << 1U), 0x10},
{0x66, (PORT_0_SENSOR_ADDR << 1U), 0x10},
{0x32, 0x01, 0x10}, /*Enable TX port 0*/
-----------------------

I have also programmed the Seralizer(UB953) for enabling camera sensor module path (GPIO) as below.
gAppIssUtilsUB953SerCfg_D3IMX390[IMX390_D3_SER_CFG_SIZE] = {
          {0x0D, 0x0F, 0x10},
          {0x0E, 0xF0, 0x10},    /* Enable GPIOs as output */
};

As per logs, it appears that Serlizer is not probed and below error captured through logs.

[IPU1-0]     22.247971 s: Serilaizer # 0 has I2CAddr 74 !!!
[IPU1-0]     24.614408 s:  
[IPU1-0]     24.614683 s:  i2cMdSubmitChan: i2c4 transfer to slave address 0x40 failed
[IPU1-0]     24.614805 s: src/bsp_deviceI2c.c @ Line 667:  
[IPU1-0]     24.614896 s:  I2C4: DEV 0x40: ERROR !!!  
[IPU1-0]     24.614957 s: src/bsp_deviceI2c.c @ Line 689:  
[IPU1-0]     24.615079 s:  I2C4: Error timeout 1 ms!!!
[IPU1-0]     24.615140 s:  IMX390: Sensor RegWrite Failed for regAddr c



For making above changes, we have refereed following e2e links (http://e2e.ti.com/support/arm/automotive_processors/f/1021/t/684294) . Please let me know if any changes are missing or if you need more information.


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TMDX654IDKEVM: IPC benchmarks

August 2, 2019, 12:34 am
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Part Number: TMDX654IDKEVM

Hi, I'm interested in seeing some benchmarks relating IPC like bandwidth/latency ? Is there any information relating this topic that you can share ? 

Thanks.

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TMS320DM6437Q: External memory to save image in TMS320DM6437Q

August 2, 2019, 12:42 am
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Part Number: TMS320DM6437Q

Hi ,

I want to extend external memory as64G to save image, is there recommended interface for TMS320DM6437Q to save them?

it's better to have SDIO, but I didn't find it.

thanks.

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AM4372: SPL configuration for EMAC boot

August 2, 2019, 12:53 am
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Part Number: AM4372

Hello Dear e2e-Team,

do I have to do any configurations, to activate ethernet boot on uboot-spl?

I can already boot the linux kernel from uboot. But uboot-spl prints only "trying to boot from uart" and does not load the uboot-image over ethernet.

Thanks,

m.u.

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TDA2PXEVM: Which usecase in visionSDK 03_05 can use to capture hdmi data?

August 2, 2019, 1:13 am
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Part Number: TDA2PXEVM

Hello,

We want to  capture hdmi data with  usecase in visionSDK 03_05, and display it in screen.Which usecase  we can select?

Thanks

Terence

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RTOS/TDA2EXEVM: QSPI boot mode doesn't work when AppImage_BE size is bigger than 15MB

August 2, 2019, 1:13 am
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Part Number: TDA2EXEVM

Tool/software: TI-RTOS

I'm working on the QSPI boot mode in a custom board which uses TDA2Ex SoC.

(1) SBL is flashed at the QSPI offset 0x0
(2) AppImage_BE is flashed at the QSPI offset 0x80000 using following commands:

The board supports more than 32MB of QSPI flash.

./network_ctrl.out --ipaddr 192.168.1.11 --cmd qspi_wr 0x0 QSPI_SBL

./network_ctrl.out --ipaddr 192.168.1.11 --cmd qspi_wr 0x80000 AppImage_BE

With the AppImage_BE's size is 15MB and below, it works fine without any problem.

However, when AppImage_BE's size bigger than 15MB, the data seems wrong at the offset 0xf80000 and the data area of SBL becomes wrong as well.

Few questions:

1) Why flashing AppImage_BE in different area could alter data of SBL area?

And why data at the offset 0xf80000 is wrong? (iT happens in case AppImage_BE's size is bigger than 15MB)

2) Is there any limitation regarding to length of AppImage when flashing QSPI flash using network_ctrl tool?

3) Do I need any additional configurations to flash bigger size of AppImage ?

Note:

"qspi_flash_writer" tool  also uses same QSPI driver but it works fine for such big AppImage_BE ("except qspi_flash_writer" works in M4 core whereas the network_ctrl's qspi works in A15 core)

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AM5728: usr/lib/libstdc++.so.6: no version information available

August 2, 2019, 1:37 am
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Part Number: AM5728

When I migrate the app to new sdk6.0, there are so many log like follows:

root@cr-1006:~# ./Smart
Smart: /usr/lib/libstdc++.so.6: no version information available (required by SmartDecoder)
Smart: /usr/lib/libstdc++.so.6: no version information available (required by SmartDecoder)
Smart: /usr/lib/libstdc++.so.6: no version information available (required by SmartDecoder)
Smart: /usr/lib/libstdc++.so.6: no version information available (required by SmartDecoder)
Smart: /usr/lib/libstdc++.so.6: no version informatio[18734.634911] hv892 4-0023: opened.
n available

Why this? In pdk5.3, there is no problem. Could you tell me how can I fix this?

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AM3715: Problem to receive on UART2

August 2, 2019, 1:38 am
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Part Number: AM3715

Hello,
customer has problem to receive on UART2 under Linux. No RX interrupt. There are nothing in the receive register. Transmission is ok.
UART1 works w/o problem. UART3 o, but has problems with the debug output which hangs.

The UARTs 1...3 uses the same driver „TI, omap3-uart“. The problem with the UART2 is seen with Linux and also with WinCE.

Is there any receive problem with the UART2?

 

Regards, Holger

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Linux: Beaglebone Black: receiving PRU interrupts in the ARM CPU

August 2, 2019, 1:33 am
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Tool/software: Linux

Hello everybody,

I am facing a Problem at which I need assistence. I need to implement an Interrupt from the PRU to be received in the ARM CPU using remoteproc and 4.14 Kernel.

I did not find any suitable example codes, so I am trying here. I hope someone has pieces of example code of the Interrupt initalisation for me.

Regards

Chris

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PROCESSOR-SDK-AM57X: 128MB QSPI flash support in RTOS

August 2, 2019, 1:43 am
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Part Number: PROCESSOR-SDK-AM57X

Dear Champs,

My customer is using RTOS PSDK 5.3 now, and want to check if 128MB qspi flash memory can be used.

As I know, only 16MB can be supported at boot time, and 64MB can be supported in the TI-RTOS after booting, right?

The target qspi flash memory is S70FL01GS with 128MB size and there are 2 CS pins to access full 128MB region as below.

could you please let me know if this CS pin can be controlled in the TI-RTOS qspi driver?

is there any way to access full 128MB regions of qspi flash memory with CS pin control?

Thanks and Best Regards,

SI.

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LINUXSDK-AM35X: TI SDK 06.00.00.07 make error

August 2, 2019, 2:09 am
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Part Number: LINUXSDK-AM35X

Hello,
I download new TI SDK 06.00.00.07. After installing ./setup script and run make I get an error

make[1]: directory entry «/home/andrey/ti-processor-sdk-linux-am335x-evm-06.00.00.07/example-applications/matrix-gui-browser-2.0»
/bin/sh: 51: export: --sysroot: bad variable name
Makefile.build:10: recipe execution error for target «qmake»
make[1]: *** [qmake] error 2
make[1]: exit from the catalog «/home/andrey/ti-processor-sdk-linux-am335x-evm-06.00.00.07/example-applications/matrix-gui-browser-2.0»
Makefile:123: recipe execution error for target  «matrix-gui-browser»
make: *** [matrix-gui-browser] error 2

I checked the variable $LDFLAGS in the file environment-setup contains the correct path. 

What could be the problem? I use ubuntu 16.04 LTS. Thanks!

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AM5728: McSPI4 MOSI issue

August 2, 2019, 2:22 am
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Part Number: AM5728

Hello,


we are trying to use the BeagleBoard-X15's McSPI4 with the Linux spidev driver (TI SDK 5.03), but we get some confusing signals on the MOSI line. SCLK and CE lines are working as expected. 

Following is the Pinmux setup for McSPI4 generated with the pearl script:
{MMC3_DAT4, (M1 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat4.spi4_sclk */
{MMC3_DAT5, (M1 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat5.spi4_d1 */
{MMC3_DAT6, (M1 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat6.spi4_d0 */
{MMC3_DAT7, (M1 | PIN_OUTPUT_PULLUP)},	/* mmc3_dat7.spi4_cs0 */

The device tree node for McSPI/spidev:
&mcspi4 {
	pinctrl-names = "default";
	status = "okay";
	spidev@0{
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <48000000>;
		reg = <0x0>;
		ti,pindir-d0-out-d1-in;
		#ti,pindir-d0-in-d1-out;
		status = "okay";
	};
};

And the output on MOSI line using linux/tools/spi/spidev_test.c:



It seems like there are two signals on this pin? We are measuring directly on the expansion connectors using a Hirose FX18-60S-0.8SV15.

We also checked IO_SET4 with the same behaviour.

Another problem is, that there are no changes on the pins if we try to switch the SPI D0 and D1 pins for input and output using the out commented line in the device tree SPI node above.

Any hints on solving these problems?

Kind Regards,

Patrick

 

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PROCESSOR-SDK-OMAPL138: The transfer has suspended while f_write / f_read to / from SD Card

August 2, 2019, 2:32 am
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Part Number: PROCESSOR-SDK-OMAPL138

Hello,

I am using the latest SDK:

-> pdk_omapl138_1_0_9

-> bios_6_75_02_00

My previous thread: https://e2e.ti.com/support/processors/f/791/t/806556

When I try save data to SD card I occur a problem, my transfer has suspended and never will go ahead. The program is waiting for completion all the time.

When I disable cache on my project, all works fine but all operation within SD Card are very slow.

Additionally, when I set breakpoint ex. MMCSD_sendCommand(handle, &cmdObj, transaction->arg); and I set action to refresh all windows, transfer within  sd card is OK (very slow but not suspended)!

I tried various options: with enable/disable DMA, enable/disable Interrupt... always I have the same result .

I don't flush and invalidate cache because I don't use DMA.

static uint8_t SD_Buffer[262144]  __attribute__ ((aligned (CACHE_LINE_SIZE)));; /* Buffer */
static FIL fil  __attribute__ ((aligned (CACHE_LINE_SIZE)));; /* File object */

//I try write 256kB buffer
fres = f_write(&fil, SD_Buffer, sizeof(SD_Buffer), &cnt);

What should I do differently? Where is a problem?

Regards, Patryk

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AM5716: Cortex-A15 ETB

August 2, 2019, 3:13 am
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Part Number: AM5716

Hi,

Is the content of ETB redirected to CT_TBR?
Can I read and analyze that area of ​​the CT_TBR address with another core (C66x or cortexM4 etc)?
What is the size of the ETB?

Best Regards,
Shigehiro Tsuda

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