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Compiler/TDA2HG: OCMC Can't be Write Succussfully After A15 Occur XDC Assert

August 1, 2019, 4:10 am
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Part Number: TDA2HG

Tool/software: TI C/C++ Compiler

When I use OCMC memory to store some flags in my code, I find some questions about it, described as follows:

1. Occupy OCMC memory, IPU2 read and others cores plus by itself respectively. Before reading, calling Cache_inv . After writing, calling Cache_wb

2. When running, A15 occurs an XDC ASSERT error on purpose (the error is made for testing) .
[HOST ] 181.014670 s: Unhandled Exception:
[HOST ] 181.014670 s: Exception occurred in ThreadType_Task
[HOST ] 181.014670 s: Exception occured in A15 with exception type 18
[HOST ] 181.014701 s: handle: 0x837bf0d4.
[HOST ] 181.014701 s: stack base: 0x837b01e0.
[HOST ] 181.014701 s: stack size: 0x800.
[HOST ] 181.014701 s: R0 = 0xfffffff0 R8 = 0xffffffff
[HOST ] 181.014731 s: R1 = 0x00000000 R9 = 0xffffffff
[HOST ] 181.014731 s: R2 = 0x00000000 R10 = 0xffffffff
[HOST ] 181.014731 s: R3 = 0xfffffff0 R11 = 0x837b0994
[HOST ] 181.014731 s: R4 = 0xffffffff R12 = 0x837b0998
[HOST ] 181.014762 s: R5 = 0xffffffff SP(R13) = 0x82f9afb4
[HOST ] 181.014762 s: R6 = 0xffffffff LR(R14) = 0x85cc8884
[HOST ] 181.014762 s: R7 = 0xffffffff PC(R15) = 0x82f9afb4
[HOST ] 181.014792 s: PSR = 0xffffffff
[HOST ] 181.014792 s: DFSR = 0x00000a05
[HOST ] 181.014792 s: IFSR = 0x00000000
[HOST ] 181.014792 s: DFAR = 0xfffffff0
[HOST ] 181.014792 s: IFAR = 0x00000000
[HOST ] 181.014823 s: Terminating Execution...
[HOST ] 181.014823 s:
[HOST ] 181.014823 s: ### XDC ASSERT - ERROR CALLBACK START ###
[HOST ] 181.014823 s:
[HOST ] 181.014853 s: E_dataAbort: pc = 0x82f9afb4, lr = 0x85cc8884.
[HOST ] 181.014853 s:
[HOST ] 181.014884 s: ### XDC ASSERT - ERROR CALLBACK END ###
[HOST ] 181.014884 s:

3. After the error occur, finding IPU1_1 /EVE1 can’t write successfully.
A. Adding debug code and print the flag in IPU1_1 core.
B. Normal case, the print messages:
[IPU1-1] 64.817239 s: WARN | TEST pParam=0x4037FC18 isReportXDCAssert=0 tick=168
[IPU1-1] 65.017202 s: WARN | TEST pParam=0x4037FC18 isReportXDCAssert=0 tick=169
[IPU1-1] 65.217226 s: WARN | TEST pParam=0x4037FC18 isReportXDCAssert=0 tick=170
As shown， the flag tick can be pulsed normally.
C. Exception case, the print messages:
[IPU1-1] 391.426035 s: WARN | TEST pParam=0x4037FC18 isReportXDCAssert=0 tick=750
[IPU1-1] 391.626029 s: WARN | TEST pParam=0x4037FC18 isReportXDCAssert=0 tick=750
As shown， the flag tick can’t be pulsed and the value is always the same.

I need your help to solve the problem. I need OCMC memory can be work normally after A15 occur XDC ASSERT.
Thanks for your attention

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AM6546: R5F and PRU shared memory

August 1, 2019, 5:02 am
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Part Number: AM6546

Can DDR shared between R5F and PRU ? can anyone give some pointers ?

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How to Boot beagleboneblack android bbbandroid from internal mmc?

August 1, 2019, 6:07 am
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I want to boot android pre-built bbbandroid.img.xz from internal mmc its always fail to boot whereas same procedure for SD Card it boot successfully.

To flash this image into internal mmc, I boot from SD Card and find internal memory at /dev/mmcblk1. Following command I used to flash image

sudo xz -cd bbbandroid.img.xz > /dev/mmcblk1

It shows partitions correctly. But always on console only slowly CCCCC printing and stopped.

Same procedure I am following to flash image into SD Card using UBuntu host machine and sd card reader and use similar command from ubuntu host machine

sudo xz -cd bbbandroid.img.xz > /dev/sdc

For Sd card, everything ok and booting successfully

I compared partitions of SD Card and internal mmc looks exactly same.

What might be problem any have idea?

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CCS/PROCESSOR-SDK-AM335X: undeclared error

August 1, 2019, 6:27 am
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Part Number: PROCESSOR-SDK-AM335X

Tool/software: Code Composer Studio

Hi.,

i am not finding below macros

SOC_INTC_MPU_DISTRIBUTOR_BASE        (ti/pdk_am335x_1_0_15/packages/ti/csl/arch/a15/src/interrupt.c)  

SOC_INTC_MPU_PHYS_CPU_IF_BASE        (ti/pdk_am335x_1_0_15/packages/ti/csl/arch/a15/hw_intc.h)  

i  am using  processor_sdk_rtos_am335x_6_00_00_07 in this version sdk code

please any help me

thank you in advance 

Regards 

chandana 

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AM3352: Add mass storage support to USB0 from u-boot

August 1, 2019, 6:36 am
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Part Number: AM3352

Hello,

We have our design based on am3352 processor.

We have both USB connected in our board, and we can use USB1 as mass storage from u-boot

=> usb start
starting USB...
USB0:   scanning bus 0 for devices... 1 USB Device(s) found
       scanning usb for storage devices... 1 Storage Device(s) found

But we also need to use USB0 as mass storage, and according to comment in am335x_evm.h

/*
 * USB configuration.  We enable MUSB support, both for host and for
 * gadget.  We set USB0 as peripheral and USB1 as host, based on the
 * board schematic and physical port wired to each.  Then for host we
 * add mass storage support and for gadget we add both RNDIS ethernet
 * and DFU.
 */

We have changed

#define CONFIG_AM335X_USB0_MODE     MUSB_PERIPHERAL

by
#define CONFIG_AM335X_USB0_MODE    MUSB_HOST

But it is still not working. What else we need to change to "add mass storage" support to USB0 ?

Best regards and thank you

Angel

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AM5718: Linux support for LCD display

August 1, 2019, 6:44 am
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Part Number: AM5718

Hi,

We have a custom AM5718 board with a LCD, connected through LVDS.

LCD part Number : G065VN01 V2

Processor SDK: ti-processor-sdk-linux-am57xx-evm-05.01.00.11

Linux Version: 4.14

I have following queries about this.

1. Does it work with existing Linux which works fine with AM5718 IDK?

2. If not, what and all changes has to be done in Linux?

3. Also dts files to be modified

Regards,

Noufal P

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Compiler/TMDSDSK6713: Problem in Implementing Higher order Filter

August 1, 2019, 2:29 am
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Part Number: TMDSDSK6713

Tool/software: TI C/C++ Compiler

Respected Members,

                                 I am trying to implement higher order Fir filter using Circular buffer.I found out this example from book named "Digital Signal Processing and Applications with the TMS320C6713 and TMS320C6416 DSK"

This example uses .asm file to implement Filter. when i implement this example it is just giving me noise. my task is to implement some higher order filter of 200 or more. i am attaching my code ,asm file and screen shots of oscilloscope and signal generator. please let me know where is problem. i also tried to implement fir lowpass filter using blackmann window. but its just noise

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RTOS/TDA2HG: Unable to execute function Bsp_platformSetPllFreq() correctly

August 1, 2019, 7:05 am
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Part Number: TDA2HG

Tool/software: TI-RTOS

I am using PROCESSOR_SDK_VISION_03_06_00_00_setuplinux to develop a custom board.

I have been able to run the uscases under HLOS before.Now I need to run uscases under RTOS.

Now there is a problem with the function Bsp_platformSetPllFreq().

I followed this function and found the point where the error occurred.

(Please visit the site to view this file)

This is the file where the error occurred.

I know that the boot of the RTOS system is different from the HLOS system. I want to know where the RTOS sets the phase-locked loop. Why does it cause the current problem?

regards,

chengbo

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DRA829: USB signal specification

August 1, 2019, 7:35 am
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Hello,

Could you provide the DRA829 USB signals specification below?

 

[1] Could you provide the USB_VBUS voltage level to detect VBUS_ON?

[2] (just confirmation) The IO voltage value of USB_VBUS pin description is 5.0V, is this correct?

[3] If you have draft specification of USB2PHY buffer type, could you provide it?

Regards,

Takeo

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DRA80M: DDR clocking / PLL3

August 1, 2019, 10:48 am
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Part Number: DRA80M

Per  a customer question, could you please provide the list of registers that need to be modified for the configuration of the DDR PLL. (Especially, the decrease of the clock frequency) 

According to TRM, DDR system is integrated from PLL3.

1. Is it correct that the only registers that control the value of the clock of the DDR is PLL3_PLL_FREQ_CTRL0 (M and N parts)?

2. Which registers from the DDRPHY should be considered as well for the change of PLL?

John

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AM3354: USB gadget is not recognized by host

August 1, 2019, 11:24 am
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Part Number: AM3354

After resolving this issue, I was able to load g_ether / g_mass_storage, but now my host computer isn't recognizing the SBC as a gadget device.

I'm watching dmesg on the host computer, and don't see any information when I plug in / unplug the SBC.

Here's what I'm running on the SBC:

dd bs=1M count=64 if=/dev/zero of=/backing_file
modprobe g_mass_storage file=/backing_file

And here's the output from dmesg:
~# dmesg | tail
[  921.136718] LUN: file: /backing_file
[  921.136732] Number of LUNs=1
[  921.136761] g_mass_storage gadget: adding config #1 'Linux File-Backed Storage'/bf1510d4
[  921.137186] g_mass_storage gadget: adding 'Mass Storage Function'/de5dad80 to config 'Linux File-Backed Storage'/bf1510d4
[  921.140897] g_mass_storage gadget: I/O thread pid: 1322
[  921.140964] g_mass_storage gadget: cfg 1/bf1510d4 speeds: high full
[  921.140978] g_mass_storage gadget:   interface 0 = Mass Storage Function/de5dad80
[  921.141013] g_mass_storage gadget: Mass Storage Gadget, version: 2009/09/11
[  921.141029] g_mass_storage gadget: userspace failed to provide iSerialNumber
[  921.141039] g_mass_storage gadget: g_mass_storage ready

Running /proc/interrupts doesn't show any interrupts for musb-hdrc.0 / musb-hdrc.1, which I would think there would be if the physical connection is being made:

# cat /proc/interrupts
           CPU0       
 16:      61879      INTC  68 Level     gp_timer
 18:          0      INTC   3 Level     arm-pmu
 20:       1561      INTC  12 Level     49000000.edma_ccint
 22:         23      INTC  14 Level     49000000.edma_ccerrint
 26:          0      INTC  96 Level     44e07000.gpio
 27:          0      INTC  98 Level     4804c000.gpio
 28:          0      INTC  32 Level     481ac000.gpio
 29:          0      INTC  62 Level     481ae000.gpio
 30:       3212      INTC  72 Level     OMAP UART0
 31:       4250      INTC  73 Level     OMAP UART1
 35:          3      INTC  71 Level     4802a000.i2c
 36:          4      INTC  30 Level     4819c000.i2c
 37:         13      INTC  64 Level     mmc0
 38:       5371      INTC  28 Level     mmc1
 39:      55156      INTC  29 Level     mmc2
 47:          0      INTC  75 Level     rtc0
 48:          0      INTC  76 Level     rtc0
 49:      64578      INTC  36 Level     tilcdc
 52:          0      INTC  80 Level     48038000.mcasp_tx
 53:          0      INTC  81 Level     48038000.mcasp_rx
 54:          0      INTC 111 Level     48310000.rng
 55:          1      INTC  37 Level     SGX ISR
 57:          1      INTC  18 Level     musb-hdrc.0
 58:          1      INTC  19 Level     musb-hdrc.1
 60:          0  44e07000.gpio   6 Edge      48060000.mmc cd
 61:          0      INTC   7 Level     tps65218
Err:          0


I ran the script from this topic, here is the output:
Linux dorado 4.14.40-ti-jumpnow #1 PREEMPT Wed Jul 31 23:53:48 UTC 2019 armv7l armv7l armv7l GNU/Linux
USB is initialized
usb@47401000: host, okay
usb@47401800: otg, okay

Gadget Kernel Config: g_ether is enabled
Gadget Kernel Config: g_mass_storage is enabled
Gadget Kernel Config: g_serial is enabled
gadget driver loaded: (none)

The list of USB gadget drivers installed:
/lib/modules/4.14.40-ti-jumpnow/kernel/drivers/usb/gadget/:
function/
legacy/
libcomposite.ko
udc/

/lib/modules/4.14.40-ti-jumpnow/kernel/drivers/usb/gadget/function:
u_ether.ko
u_serial.ko
usb_f_acm.ko
usb_f_ecm.ko
usb_f_ecm_subset.ko
usb_f_eem.ko
usb_f_fs.ko
usb_f_hid.ko
usb_f_mass_storage.ko
usb_f_ncm.ko
usb_f_obex.ko
usb_f_rndis.ko
usb_f_serial.ko
usb_f_uvc.ko

/lib/modules/4.14.40-ti-jumpnow/kernel/drivers/usb/gadget/legacy:
g_acm_ms.ko
g_cdc.ko
g_ether.ko
g_ffs.ko
g_hid.ko
g_mass_storage.ko
g_multi.ko
g_serial.ko
gadgetfs.ko

/lib/modules/4.14.40-ti-jumpnow/kernel/drivers/usb/gadget/udc:
bdc/
dummy_hcd.ko
fotg210-udc.ko
fusb300_udc.ko
gr_udc.ko
m66592-udc.ko
mv_u3d_core.ko
mv_udc.ko
net2272.ko
pxa27x_udc.ko
r8a66597-udc.ko
snps_udc_core.ko
snps_udc_plat.ko
udc-xilinx.ko

/lib/modules/4.14.40-ti-jumpnow/kernel/drivers/usb/gadget/udc/bdc:
bdc.ko


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AM6546: dts memory size in u-boot

August 1, 2019, 1:15 pm
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Part Number: AM6546

Hi champs

have a question regarding dts file and memory size how to change the memory size to smaller value?

In the current dts file we have the following. From my understanding for the R5 why have 2GB of memory for R5? can that 2GB be used for linux also it does not look like it?

address= 0x80000000 and the size is 0x80000000

For a53 we have

starting address = 0x880000000 size is 0x80000000

The reserved is for op-tee which is located at 0x9e800000 this is part of the R5 memory space correct? Do i really need this can i just assign all the memory to A53? Why is this needed for the op-tee. I thought op-tee is part of the spl and it is running in the internal memory

memory@80000000 {
device_type = "memory";
/* 4G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
<0x00000008 0x80000000 0x00000000 0x80000000>;
};

reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: secure_ddr@9e800000 {
reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};

What i like to do is if i have 512MB of memory on my board then what is going to be my memory and reserved-memory? I like to maximum the memory for linux,  Any suggestions would be great. 

Thanks

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AM3357: Accessing GPIO Pins on AM335X

August 1, 2019, 1:31 pm
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Part Number: AM3357

Hello,

I want to know how can i control user led within C program on am335x. Where is the driver file located on the filesystem?

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TDA2EVM5777: radar SDK AoA in 4 AWR12 Cascade Object Detect Use Case

August 1, 2019, 2:07 pm
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Part Number: TDA2EVM5777

How does the angle of arrival function work in radarDspCascadeMimoAoa_priv.c? Is the any reference material avaible that explains  this alg_fxns alg_plugin?

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PROCESSOR-SDK-DRA7X: 4ch mix in/BT.1120 16bit to VIP Capture

August 1, 2019, 5:40 pm
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Part Number: PROCESSOR-SDK-DRA7X

Dear Sir, 

I have a 

  • 4 Channel video sensor input to one video decoder.
  • This decoder will output one channel YUV422 BT.1120 16bit 74.25MHz to VIP captuer in TDA2.

I need to confirm this kind application had verified, and the performace is fine.

And, please let me know how to cahnge the VIP setting on PROCESSOR_SDK_VISION_03_05_00_00.

Thanks!

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AM3352: About VDD_MPU Voltage issue

August 1, 2019, 6:57 pm
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Part Number: AM3352

Hi  SIr 

We used AM3352 1G with TPS65910 for design.

and followed PMIC default setting. 

We measure the voltage of VDD_MPU is 1.35V for 1GHz. 

Do you know what is the max. ripple tolerance for AM3352 ? 

thanks 

BR

Yimin

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[TDA4M] Supporting raw RCCB image sensors

August 1, 2019, 7:11 pm
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Hi,

There're only 4 types for sensor image formats in SDK v0.9

uint8_t sensor_img_phase; /*!<Image Format : BGGR = 0, GBRG = 1, GRBG = 2, RGGB = 3 */

When will the RCCB format be supported in TDA4 SDK?
RCCB may be working by using RGGB format instead of RCCB, but I'm not sure AWB and other features can work properly.

Regards,
HJ

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TMS320C6678: DDR3 CS1 is not correct at 1000MHz-1600MHz

August 1, 2019, 8:23 pm
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Part Number: TMS320C6678

Hello Champs,

C6678 DDR3 controller CS0, CS1 are connected with 5 16bit DDR3 to combine 64bit data width respectivlely,   512MB ( one of them is ECC) per piece. 

When the DDR3 operated at 800MHz-1000MHz, the CS0, CS1 space work correctly. 

When the DDR3 operated at 000MHz-1600MHz, the CS0 space works correctly. But CS1 space works incorrectly, the high 32bit data read/write is wrong while the low 32bit data read/write is correct. 

Below is the timing wave for CK1 and WE at 1600MHz. 

How to adjust the relationship between clock and command line? That is, how to adjust the phase of clock, e.g. 1/4 phase. 

Thanks.
Rgds
Shine

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CCS/TMS320C6678: C6678 runs NC_NETSTOP(1) but get "double free"

August 1, 2019, 8:31 pm
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Part Number: TMS320C6678

Tool/software: Code Composer Studio

Hi. everybody,

below is what I used:

C6678EVM

CCS8,

NDK3.40.1.01

pdk-05.02.00.10 or pdk-06.00.00.07

When I use NC_NETSTOP(1) to restart the NDK, it fails and get error "double free"

please tell me how to fix it,tks!

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AM5718: A setup guide for TIDEP-0096: High-Availability Seamless Redundancy Ethernet Reference Design for Substation Automation for Linux

August 1, 2019, 10:41 pm
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Part Number: AM5718

Hello,

I understood the document explains HSR/PRP on Linux-RT.

Can I ask whether its setup guide is available?

TI Designs: TIDEP-0096

High-Availability Seamless Redundancy Ethernet Reference Design for Substation Automation for Linux

http://www.ti.com/tool/TIDEP-0096

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