Part Number: BEAGLEBK
Hi,
Is there any way to adapt ICE AMIC110 / ICEv2 PDK examples for BBB as I'm planning to use PRU-ICSS for my adapter and a sample code will be great at the beginning.
Best regards
przemek
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BEAGLEBK: PRU-ICSS examples
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CCS/PROCESSOR-SDK-AM335X: GPIO issue
Part Number: PROCESSOR-SDK-AM335X
Tool/software: Code Composer Studio
Hi.,
please any one check the code flow what i posted below,
my issue is LED is not glowing ,
void Gpio_test()
{
GPIO1ModuleClkConfig();
GPIO1Pin4PinMuxSetup();
GPIOModuleEnable(SOC_GPIO_1_REGS);
GPIOModuleReset(SOC_GPIO_1_REGS);
GPIODirModeSet(SOC_GPIO_1_REGS, GPIO_LED_PIN_NUMBER, 0); // GPIO_LED_PIN_NUMBER = 6
GPIOPinWrite(SOC_GPIO_1_REGS, GPIO_LED_PIN_NUMBER, 1); // GPIO_LED_PIN_NUMBER = 6
}
thank you in advance
Regards
chandana
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AM3358: How to modify&debug SBL(MLO) with CCS" by using TI-RTOS(PROCESSOR-SDK-RTOS-AM335X)
Part Number: AM3358
Hello, TI Experts,
Our customer sent us questions about "how to modify&debug SBL(MLO) with CCS" by using TI-RTOS(PROCESSOR-SDK-RTOS-AM335X).
They want to debug SBL for AM335x with CCS like below link.
http://processors.wiki.ti.com/index.php/Creating_a_CCS_Project_for_SBL_on_AM572x_GP_EVM
But they couldn't find same information for AM335x like above link.
Question:
- Could you tell us the proper link/information to debug SBL(MLO) for AM335x with CCS like this?
We would also appreciate if you tell us the recommended way to modify&debug SBL(MLO) with CCS" by using TI-RTOS(PROCESSOR-SDK-RTOS-AM335X).
Best regards,
↧
WEBENCH® Tools/TDA2EVM5777: PROCESSOR_SDK_VISION_02_10_00_00_setuplinux .bin download
Part Number: TDA2EVM5777
Tool/software: WEBENCH® Design Tools
Hi,
Where to download VSDK 2.10.
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OMAPL138B-EP: Is SYSLINK supported on ARM9
Part Number: OMAPL138B-EP
From the SYSLINK release note, on L138, ARM run Linux, DSP run SYSBIOS, does it mean SYSLINK is not supported on ARM or just not verified?
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CCS/DRA745: test load ddr test out, run error
Part Number: DRA745
Tool/software: Code Composer Studio
Hi,expert,
I want to run DDR test software on J6 EVM. CCS show an error as below:
Cortex_M4_IPU1_C0: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence In Progress... <<<--- Cortex_M4_IPU1_C0: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence DONE! <<<--- Cortex_M4_IPU1_C1: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence In Progress... <<<--- Cortex_M4_IPU1_C1: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence DONE! <<<--- Cortex_M4_IPU2_C0: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence In Progress... <<<--- Cortex_M4_IPU2_C0: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence DONE! <<<--- Cortex_M4_IPU2_C1: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence In Progress... <<<--- Cortex_M4_IPU2_C1: GEL Output: --->>> DRA7xx Cortex M4 Startup Sequence DONE! <<<--- C66xx_DSP1: GEL Output: --->>> DRA7xx C66x DSP Startup Sequence In Progress... <<<--- C66xx_DSP1: GEL Output: --->>> DRA7xx C66x DSP Startup Sequence DONE! <<<--- C66xx_DSP2: GEL Output: --->>> DRA7xx C66x DSP Startup Sequence In Progress... <<<--- C66xx_DSP2: GEL Output: --->>> DRA7xx C66x DSP Startup Sequence DONE! <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Cortex A15 Startup Sequence In Progress... <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Cortex A15 Startup Sequence DONE! <<<--- CortexA15_1: GEL Output: --->>> DRA7xx Cortex A15 Startup Sequence In Progress... <<<--- CortexA15_1: GEL Output: --->>> DRA7xx Cortex A15 Startup Sequence DONE! <<<--- ARP32_EVE_1: GEL Output: --->>> Configuring EVE Memory Map <<<--- ARP32_EVE_1: GEL Output: --->>> EVE Memory Map Done! <<<--- ARP32_EVE_2: GEL Output: --->>> Configuring EVE Memory Map <<<--- ARP32_EVE_2: GEL Output: --->>> EVE Memory Map Done! <<<--- ARP32_EVE_3: GEL Output: --->>> Configuring EVE Memory Map <<<--- ARP32_EVE_3: GEL Output: --->>> EVE Memory Map Done! <<<--- ARP32_EVE_4: GEL Output: --->>> Configuring EVE Memory Map <<<--- ARP32_EVE_4: GEL Output: --->>> EVE Memory Map Done! <<<--- IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<--- CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress... CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<---- CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> --- CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<---- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do. DRA7xx_MULTICORE_EnableAllCores() cannot be evaluated. Could not write 0x4AE06510: target is not connected at *((unsigned int *) ((cpu_num==1) ? (((0x4AE00000+0x6000)+0x500)+0x10) : (((0x4AE00000+0x6000)+0x700)+0x210)))=(unsigned int) 0x7 [DRA7xx_multicore_reset.gel:12] at IPUSSClkEnable(1) [DRA7xx_multicore_reset.gel:324] at IPU1SSClkEnable_API() [DRA7xx_multicore_reset.gel:292] at DRA7xx_MULTICORE_EnableAllCores()CortexA15_0: GEL Output: --->>> DRA7xx Target Connect Sequence Begins ... <<<--- CortexA15_0: GEL Output: Core Reset has occurred. CortexA15_0: GEL Output: --->>> DRA7xx PG2.0 GP device <<<--- CortexA15_0: GEL Output: --->>> The core is in non-SECURE state. <<<--- CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<--- CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking... CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE! CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: PER DPLL already locked, now unlocking CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE! CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking.... CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE! CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE! CortexA15_0: GEL Output: EVE DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: EVE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE! CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<--- CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress... CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE! CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers CortexA15_0: GEL Output: as per HW leveling output CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from CortexA15_0: GEL Output: PHY_STATUSx registers CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers CortexA15_0: GEL Output: as per HW leveling output CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from CortexA15_0: GEL Output: PHY_STATUSx registers CortexA15_0: GEL Output: Two EMIFs in interleaved mode - (1GB total) CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Begin All Pad Configuration for Vision Platform <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Begin All Pad Configuration for RGMII usage on EVM Platform <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Begin GMAC_SW MDIO Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> DRA7xx End GMAC_SW MDIO Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Begin GMAC_SW RGMII0 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> DRA7xx End GMAC_SW RGMII0 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Begin GMAC_SW RGMII1 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> DRA7xx End GMAC_SW RGMII1 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> DRA7xx End All Pad Configuration for RGMII usage on EVM Platform <<<--- CortexA15_0: GEL Output: --->>> DRA7xx End All Pad Configuration for Vision Platform <<<--- CortexA15_0: GEL Output: --->>> DRA7xx Target Connect Sequence DONE !!!!! <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE3SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE3SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE4SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE4SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<--- Cortex_M4_IPU1_C0: Can't Run Target CPU: (Error -1268 @ 0x1090001) Device is locked up in Hard Fault or in NMI. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.2.0.00004) CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE3SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE3SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> EVE4SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 1: 0x00000000 --> 0x40500000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 2: 0x80000000 --> 0x80000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 3: 0x81000000 --> 0x81000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 4: 0x82000000 --> 0x82000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 5: 0x83000000 --> 0x83000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 6: 0x84000000 --> 0x84000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 7: 0x85000000 --> 0x85000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 8: 0x86000000 --> 0x86000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 9: 0x87000000 --> 0x87000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 10: 0x40000000 --> 0x40000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 12: 0x45000000 --> 0x45000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 13: 0x48000000 --> 0x48000000 CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 14: 0x42000000 --> 0x42000000 CortexA15_0: GEL Output: --->>> EVE4SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<--- Cortex_M4_IPU1_C0: Can't Run Target CPU: (Error -1268 @ 0x1090001) Device is locked up in Hard Fault or in NMI. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.2.0.00004)
Could you help to check ?
Br, Widic
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[TDA4M] Adding new cameras and DCC tuning tools
Hi,
I couldn't find camera related documents in TDA4 SDK v0.9.
Can you provide following documents or tools? If not right now, when will it be available?
1) documents about adding new sensors
2) DCC tool for TDA4 and related documents
Regards,
HJ
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66AK2H14: In DDR3 non-cacheable write accesses from DSP are made through write buffer ?
Part Number: 66AK2H14
Hi everyone!
I have strange result in some test, I was wondering if I have a good understanding of DDR3 cacheability.
My question is:
In DDR3 non-cacheable write accesses from DSP are made through write buffer ?
Regards,
François
↧
TDA2P-ACD: GPIO interrupt delay
Part Number: TDA2P-ACD
Hi
We are using PWM module to generate 60 Hz signal. Same signal is routed back to TDA.
Further, we are using GPIO interrupt (GPIO_4) for detecting rising edge of PWM. Inside ISR we are time-stamping
this event. So, difference between two consecutive interrupts should be 16 667 us. But, in our case, time difference is
always very close to 16 000 us or 17 000 us. For example, if we change PWM signal to 50 Hz 100 Hz, or any frequency which
period is rounded to 1 ms (eg. 20 ms or 10 ms) time-stamp is very precise. So, our conclusion that this could be related
to GPIO interrupt latency and GPIO clock. Is this correct? What is clock frequency used for GPIO_4 and is it possible to change it.
Please, give us some hint, our customer is waiting for replay.
Time-stamp function returns time in micro seconds.
Best regards,
Stefan.
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↧
PROCESSOR-SDK-AM437X: DP83867 not detected
Part Number: PROCESSOR-SDK-AM437X
Working on AM437x custom board.
At u-boot able to detect the PHY.
Ping is happening.
At linux not able to detect the phy.
log is shared
dts for ethernet as below
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_crs.rmii1_crs */
AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_rxerr.rmii1_rxerr */
AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_txen.rmii1_txen */
AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_rxdv.rmii1_rxdv */
AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_txd3.rgmii1_txd3 */
AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_txd2.rgmii1_txd2 */
AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_txd1.rmii1_txd1 */
AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_txd0.rmii1_txd0 */
AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_txclk.rmii1_tclk */
AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_rxclk.rmii1_rclk */
AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_rxd3.rgmii1_rxd3 */
AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_rxd2.rgmii1_rxd2 */
AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_rxd1.rmii1_rxd1 */
AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_rxd0.rmii1_rxd0 */
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM4372_IOPAD(0x948, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* 1.5k PU 3v3 */
AM4372_IOPAD(0x94c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7)
>;
};
&mac {
slaves = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
interrupt-parent = <&gpio1>;
interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
status = "okay";
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii-txid";
};
&phy_sel {
rmii-clock-ext;
};
(Please visit the site to view this file)
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AM6548: IDK as PCIe endpoint
Part Number: AM6548
Hi,
A customer of mine would like to use the AM6548 IDK as PCIe endpoint. Will this work with a simple adapter cable connected to a host PC? Or are there any changes on the board required?
2nd question: when operating as endpoint, will we offer drivers for the host side (x86 PC using Windows or Linux)?
Thanks,
Robert
↧
コンパイラ/ TMS320C6747： About many occurrences of "identifier *** is undefined".
Part Number: TMS320C6747
Tool/software: TI C/C++ Compiler
Hello Mr. Rahul
I am troubled with the error of attached log now. (Undefined as before)
Here is the process.
Dell Vostro Core_i7 / 3.4GHz / 8GB / 900GB_HDD (400GB free)
I made win7 with VirtualBox in win10.
I have installed CCS5.5.0.00077_win32.
Installed C6747_BIOSPSP_01_30_01.
Installed EDMA3_LLD_BIOS5_01_11_00_03.
Installed ti_cgt_c6000_8.3.1_windows_installer.exe
Set this compiler selection in Project_Propaties_General.
A meta-data_error occurs when importing a source file set. (This is the same as the other day)
Create a new project empty, and drag and drop source files to create a build project. However, many occurrences of "identifier" Uns "is undefined".
The attached 3 files are as follows.
log, compiler selection, and Hierarchical top file
(Please visit the site to view this file)
Best, regards
Suzuki
2019_0731_19: 00 @ japan
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AM3359: Qt application on ICE
Part Number: AM3359
Respected sir,
I was able to run the hello world application from Linux SDK and RTOS SDK on AM3359 ICE. Now i want to run Qt based application on AM3359 ICE as my project will be on Qt. But i am not able to find any user guide or getting started guide for running Qt based appliacation on above mentioned device. So can anybody share the Document /link/Example/Process for the same??
Regards,
Digvijay
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↧
TDA2PXEVM: git am ../linux-kernel-addon/earlyboot-kernel-patches/* failed
Part Number: TDA2PXEVM
Hi,
I want to apply the earlyboot-kernel-patches for kernel.But it apply failed.My vision SDK version is 3.07.
Here's the apply log.
git am ../linux-kernel-addon/earlyboot-kernel-patches/* 应用：dra7xx: Kernel Optimizations for early-use-case enablement error: 打补丁失败：ti_config_fragments/auto.cfg:50 error: ti_config_fragments/auto.cfg：补丁未应用 打补丁失败于 0001 dra7xx: Kernel Optimizations for early-use-case enablement 失败的补丁文件副本位于：.git/rebase-apply/patch 当您解决这一问题，执行 "git am --continue"。 如果您想要跳过这一补丁，则执行 "git am --skip"。 若要复原至原始分支并停止补丁操作，执行 "git am --abort"。
Could you give some help?
Regards
Ll
↧
Compiler/TMS320C6678: 6678 optimized code performance issue
Part Number: TMS320C6678
Tool/software: TI C/C++ Compiler
Hello
i have two question to ask.
we tried different size of FFT (double, float, int32) inside dsplib of c6678 (version 3.4.0.0). we used TSCL of dsp to measure execute time of FFT. in all cases our measured time was 2 to 2.5 times greater than numbers reported in dsplib benchmark, here is first question:
1- what is source of this mismatch between our measured execution time and TI reported times (we implement our test according to all of TI recommendations)?
we also compared TI benchmark result of dsplib for 6455 to 6678. and Here is second question:
2- considering all of improvement in 6678, for example addition of more multiplier and ..., how comes that 6455 and 6678 performance are approximately the same (based on TI report numbers)?
↧
TDA2EVM5777: Alg Plugin Creation on Linux
Part Number: TDA2EVM5777
Hello everyone,
I am creating an alg-plugin for my usecase over linux.
UseCase :- Capture -> Alg_ABC (DSP1) -> Display_M4 (IPU1_0)
I have referred FrameCopy for the development and followed the same steps for Linux. But when I include my plugin in cfg.mk at apps/configs path ,where all plugins are included for build , it is searching for SRC.MK file. But it is not being included in the plugin folder for the development over Linux (as per referred FrameCopy).
Am I doing something wrong in here? Do I need to put the plugin folder at rtospath and create SRC.MK file specifying path for build ?
Following error has been given on the terminal :-
Makefile:51: /home/linux/Documents/SourceCode/vision_sdk/apps/src/rtos/alg_plugins/ABC/SRC_FILES.MK: No such file or directory
make[4]: *** No rule to make target '/home/linux/Documents/SourceCode/vision_sdk/apps/src/rtos/alg_plugins/ABC/SRC_FILES.MK'. Stop.
MAKEFILE.MK:9: recipe for target 'libs' failed
make[3]: *** [libs] Error 2
Makefile:200: recipe for target 'app_alg_plugins' failed
make[2]: *** [app_alg_plugins] Error 2
Makefile:36: recipe for target 'apps' failed
make[1]: *** [apps] Error 2
Makefile:12: recipe for target 'vision_sdk' failed
make: *** [vision_sdk] Error 2
Pl provide your inputs to resolve the issue.
Regards,
Shantanu Joshi
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AM3358: Dual EMAC issue
Part Number: AM3358
Hi,
The customer connect one 100M (DP83848 (eth0)) network port and one 1000M (DP83867 (eth1)) network port by CPSW. The 100M network port can work normally. The 1000M port can be linked up, but cannot ping successfully. The device tree configuration as follows:
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
dual_emac = <1>;
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
dp83867_0: ethernet-phy@3 {
reg = <3>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
};
dp83848_0: ethernet-phy@7 {
reg = <7>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <7>;
dual_emac_res_vlan = <1>;
phy-mode = "rmii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <3>;
dual_emac_res_vlan = <2>;
phy-mode = "rgmii-id";
};
内核log如下
Configuring network interfaces...
[ 10.518385] net eth0: initializing cpsw version 1.12 (0)
[ 10.687456] NS DP83848C 10/100 Mbps PHY 4a101000.mdio:07: attached PHY driver [NS DP83848C 10/100 Mbps PHY] (mii_bus:phy_addr=4a101000.mdio:07, irq=POLL)
[ 10.701969] PHY_INTERFACE_MODE_RMII
[ 10.705494] gmii_sel:reg=0xe9
[ 10.718883] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 10.724805] 8021q: adding VLAN 0 to HW filter on device eth0
[ 10.773229] net eth1: initializing cpsw version 1.12 (0)
[ 10.789765] TI DP83867 4a101000.mdio:03: attached PHY driver [TI DP83867] (mii_bus:phy_addr=4a101000.mdio:03, irq=POLL)
[ 10.801731] AM33XX_GMII_SEL_MODE_RGMII
[ 10.805508] gmii_sel:reg=0xe9
[ 10.813426] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[ 10.819411] 8021q: adding VLAN 0 to HW filter on device eth1
[ 12.888081] _cpsw_adjust_link:mac_control=0x20
[ 12.892601] cpsw 4a100000.ethernet eth1: Link is Up - 100Mbps/Full - flow control rx/tx
[ 12.901400] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
The gmii_sel is set to 0xe9 according to the data manual register, 1000M network port will be normal when inserted and removed.
↧
↧
AM4372: EMAC boot
Part Number: AM4372
Hello dear e2e-Team,
which configurations do I have to do on my Host-PC that the ROM-Bootloader will boot the uboot-files over Ethernet? Do you have any Manuals for this?
Thanks!
m.u.
↧
AM3357: Python import error
Part Number: AM3357
Hello,
I am trying to run a python script with python on the am335x. I am getting ImportError: libboost_python-py27.so.1.62.0: cannot open shared object file: No such file or directory. How can i resolve this error. Is there way to get this library using opkg.
↧
TDA2HG: TDA2XX linux VSDK0305 IPU2 GPIO interrupt
Part Number: TDA2HG
HI master:
I have a problem on my VSDK0305,The hardware is TDA2XX.
my board boot as linux target,
now, I want make a gpio interrupt on M4[ipu2],
i follow the demo , but can't work well.
GPIO is GPIO2_6.
SDK: PROCESSOR_SDK_VISION_03_05_00_00.
We are reference processor_sdk_vision_03_05_00_00/ti_components/drivers/pdk_01_10_01_06/packages/ti/csl/example/gpio/gpio_interrupt/main.c.
processor_sdk_vision_03_05_00_00\vision_sdk\links_fw\src\rtos\links_ipu\vip_capture\captureLink_drv.c
Int32 CaptureLink_drvCreateInst(CaptureLink_Obj * pObj, UInt16 instId) //called cam_intb_init();
my code ：
void configurGpioInterrupt()
{
#if 1
CSL_xbarIrqConfigure(CSL_XBAR_IRQ_CPU_ID_IPU2,IRQ_XBAR_INST_NO,IRQ_XBAR_INDEX);
#endif
int cpuid = System_getSelfProcId();
Intc_Init();
Intc_IntEnable(interrupt_num);
Vps_printf("Intc_IntRegister interrupt_num:%d\n",interrupt_num);
Intc_IntRegister(interrupt_num, (IntrFuncPtr) gpioIsr, (void *) 0);
Vps_printf("Intc_IntRegister end\n");
Intc_IntPrioritySet(interrupt_num, 1, 0);
Intc_SystemEnable(interrupt_num);
BspOsal_registerIntr(interrupt_num,gpioIsr,(void *) 0);
}
int cam_intb_init(void)
{
//m4pid0
/*Configure interrupt controller*/
configurGpioInterrupt();
/*Reset GPIO*/
Vps_printf("GPIOModuleReset-start\n");
GPIOModuleReset(gpio_base_address);
/*Enable GPIO*/
GPIOModuleEnable(gpio_base_address);
/*Configure and enable debouncing feature*/
GPIODebounceTimeConfig(gpio_base_address, 0xFF);
Vps_printf("GPIODebounceTimeConfig\n");
GPIODebounceFuncControl(gpio_base_address, gpio_pin,
GPIO_DEBOUNCE_FUNC_ENABLE);
Vps_printf("GPIODebounceFuncContro\n");
GPIOIntTypeSet(gpio_base_address, gpio_pin,GPIO_INT_TYPE_FALL_EDGE);
Vps_printf("GPIOIntTypeSet\n");
/* Set pin direction as input*/
GPIODirModeSet(gpio_base_address, gpio_pin, GPIO_DIR_INPUT);
Vps_printf("GPIODirModeSet\n");
/*Clear interrupt*/
GPIOPinIntDisable(gpio_base_address, GPIO_INT_LINE_1, gpio_pin);
Vps_printf("GPIOPinIntDisable\n");
GPIOPinIntClear(gpio_base_address, GPIO_INT_LINE_1, gpio_pin);
Vps_printf("GPIOPinIntClear\n");
/*Enable interrupt*/
GPIOPinIntEnable(gpio_base_address, GPIO_INT_LINE_1, gpio_pin);
Vps_printf("GPIOPinIntEnable\n");
return 0;
}
processor_sdk_vision_03_05_00_00\vision_sdk\links_fw\src\rtos\links_ipu\vip_capture\captureLink_drv.c
Int32 CaptureLink_drvCreateInst(CaptureLink_Obj * pObj, UInt16 instId)
{
CaptureLink_VipInstParams *pInstPrm;
CaptureLink_InstObj *pInst;
Vps_CaptCreateParams *pVipCreateArgs;
Vps_CaptVipParams *pVipPrms;
Vps_CaptVipScParams *pScParams;
Vps_CaptVipOutInfo *pVipOutPrm;
Vps_VipPortConfig *pVipPortCfg;
CaptureLink_OutParams *pOutPrm;
System_LinkChInfo *pQueChInfo;
UInt16 queId, queChId, outId;
Int32 status;
Int32 nRetVal = 0;
Fvid2_DataFormat dataFormat;
cam_intb_init(); //called gpio interrupt But the IPU can't start.
my log:
[HOST] [HOST ] Enter Choice:
[HOST] [HOST ]
1
[HOST] [HOST ] 22.276215 s:
[HOST] [HOST ] 22.276764 s:
[HOST] [HOST ] USE_SHANGFU_PANEL_1440x810
[HOST] [HOST ] 22.276764 s: ChainsCommon_SetDctrlConfig displayType=5, displayWidth=1440,displayHeight=810 debug
[HOST] [HOST ]
[HOST] [IPU2 ] 22.276428 s: CHAINS: ChainsCommon_MultiCam_StartCaptureDevice
[HOST] [IPU2 ] 22.276550 s: status != SYSTEM_LINK_STATUS_SOK
[HOST] [IPU2 ] 22.325687 s: CAPTURE: Create in progress !!!
[HOST] [IPU2 ] 22.337034 s: Intc_IntRegister interrupt_num:52
Ths.
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