Part Number: PROCESSOR-SDK-AM65X
Hi TI,
Can someone tell me how to add the usbmon module to my linux distro?
Thank you,
SC
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PROCESSOR-SDK-AM65X: AM65xx missing usbmon module
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TMS320DM8127: How to manually set exposure in TMDSCSK8127 board with IPNC RDK 3.9.1?
Part Number: TMS320DM8127
Hi, I'm using camera starter kit in full feature mode with AR0331 sensor. How can I manually set exposure time bypassing 2A engine during RTP streaming (2A disabled in web interface) ? I Board is new for me and all documentation I got from TI site.
Is there an easy way to change exposure by sending i2c commands to sensor from linux console? (smth like i2c_send <camera_id> <reg> <value>)
Thanks in advance.
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AM5716: Linux GMAC/PRU PTP 1PPS input support without BC?
Part Number: AM5716
The latest Linux processor SDK version 6 supports 1PPS signals on both GMAC and PRU HSR/PRP ports. The test setup for 1PPS measurements using IDK is well documented. But it explains 1PPS inputs (latch) for PTP BC (Boundary Clock) only when, say, GMAC clock can sync to PRU clock or vice verse, and BC driver controls the direction.
In my setup I do not need the BC. I want to have ordinary clock PTP master on any of interfaces (GMAC or PRP/HSR) which is driven by external GPS 1PPS signal: GPS 1PPS -> PRU/GMAC 1PPS latch. This configuration is not documented.
Standard Linux way is to route 1PPS via GPIO (or other port pins). It is hardware independent, but it uses GPIO interrupts and involves kernel. This will have unacceptable jitter. So a hardware 1PPS processing using timers is much better, but is this supported? Will 1PPS inputs work if fed to latch inputs to sync PTP clocks without BC driver? I do not need to control which 1PPS is active (what BC driver does). But I am not sure if this configuration is possible and guaranteed to work.
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CCS/TMDSLCDK6748: LCDK6748
Part Number: TMDSLCDK6748
Tool/software: Code Composer Studio
To whom it may concern,
I'm using the starterware to get started with the LCDK6748 board. I can not find an example associated with the Line in\out interface. I need this for signal processing application and a course development. I was wondering if you could help me in this regard.
It is to mention that the old projects I have in hand have been written for dsk6713 and once I want to load the program I get memory verification errors and load gets failed.
I appreciate your help in this regard.
Regards,
Pourya
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AM3354: AM3354 EMI Test
Part Number: AM3354
Hi
1. Question introduction
Our product have done EMC test And we found that whether connected with PHY module or peripherals or the pure power-on state will approach or exceed the critical EMC value at some frequency points.And only three RS485 and one Gigabit Network ports on board;
2. Specific phenomena
(1) Running test program status: 485 pairs of tests, gigabit network port Ping routing; EMI Test result as below:
(2) Pure power-on state, do not run the test program; 175M is close to the critical point;
So regardless of whether the test program runs or not, 175M and other frequency points are basically critical or exceed the standard.
A. CPU crystal is 24M, which function module may be doubled to 175M?
B. Any other suggestions for rectification?
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AM3354: MDC wave form on booting-up
Part Number: AM3354
Hi.
I am using AM3354 and ethernet phy DP83822. (Custom board based on AM335x EVM)
Processor SDK : 04.03.00.05
I am investigating MDC issue.
Wave form we observe is below.
From the top are Main power, EthPHY reset, MDC, System reset.
System reset is rising up after 200ms from rising-up Main power, and soon EthPHY reset will be.
MDC signal may have Hi-Z state. (intermediate voltage on both Lo and Hi state)
After 6 sec from Main power on, kernel starts, and generated MDC 1 pulse. But I don't know their context.
I have 2 questions.
(1) Why does MDC pin have Hi-Z state? I think it may be initial state of MDC pin...
And no problem to induce by main power suply or stay Hi-Z state?
(2) Why is there 1 MDC pulse on kernel startin? Is this pulse needed for initializing PHY?
Regards.
Nishihashi
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TDA2PXEVM: How to do IODelay Recalibration for QSPI in TDA2Px
TDA2PXEVM: How to do IODelay Recalibration for QSPI in TDA2Px
Hi All
We use TDA2Px with QSPI boot mode [SBLLIB_BOOT_MODE_QSPI], the default QSPI clock is 48MHz [QSPI_SCLK_FREQ_48MHz], we need to change this clock to 76.8MHz [QSPI_SCLK_FREQ_76_8MHz]
We checked the SDK code [SBLUtilsScaleIODelay] and find a default config about [gPadDelayConfigObj], it comes from [gPadDelayConfigCommon_1_0] which seems to be created by clock tree tools
The document [Technical Reference Manual] about [26.4.4.1.4 SPI Clock Generator] contents has no information about [IODelay Recalibration]
The document [TDA2Px ADAS applications processor] about [5.10.6.12 QSPI] contents has information about [Manual IO Timings]
So we want to known how [IODelay Recalibration] is doing when config QSPI clock to [QSPI_SCLK_FREQ_76_8MHz] and how we use it?
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AM5728: Enabling SPI1 Issues
Part Number: AM5728
Hello,
I'm having some issues enabling SPI1 with the following configurations:
1.)
In U-boot-2017.1/board/ti/am57xx/mux_data.h:
const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
{SPI1_SCLK, (M14 | PIN_OUTPUT)},
{SPI1_D1, (M14 | PIN_OUTPUT)},
{SPI1_D0, (M14 | PIN_OUTPUT)},
{SPI1_CS0, (M14 | PIN_OUTPUT)}
};
2.) I have enabled CONFIG_SPI_SPIDEV in linux-kernel/arch/arm/configs/tisdk_am57xx-evm_defconfig
3.) I have modifed the device tree file as follows:
&dra7_pmx_core {
spi1_pins_s0: spi1_pins_s0 {
pinctrl-single,pins = <
0x3A4 (PIN_INPUT_PULLUP | MUX_MODE0) /* GW SPI CLIK | Ballpin A25 */
0x3A8 (PIN_INPUT_PULLUP | MUX_MODE0) /* GW SPI MISO | Ballpin F16 */
0x3AC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* GW SPI MOSI | Ballpin B25 */
0x3B0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* GW SPI CS | Ballpin A24 */
>;
};
&mcspi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_s0>;
ti,pindir-d0-out-d1-in;
spidev@1 {
spi-max-frequency = <48000000>;
reg = <0>;
compatible = "rohm,dh2228fv";
};
};
4.) When the device boots up, I am able to see /dev/spidev1.0. However, when I perform the command echo "deadbeat" >> /dev/spidev1.0, I'm not seeing any activity on the clk line, cs line, or MOSI line!
What steps am I missing?
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TDA3MV： How do I setting ISS colour to gray
Part Number: TDA3MV
Processor: TDA3
Sensor: Aptina AR0140
I have some problem wish to solve
How do I setting ISS saturation to make the colour video to gray?
Does DCC tool have upgrade version? it seems to have a lot of problems,
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AMIC110: Does the HSR/PRP protocol development on the basis of AMIC110 require the official authorization of TI and additional fees?
Part Number: AMIC110
Dear All:
Does the HSR/PRP protocol development on the basis of AMIC110 require the official authorization of TI and additional fees? Like licensing fees for protocol packages? Previously, the development of Profinet protocol using AM335X required official authorization and fees.
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TDA2E: linux vision SDK 3.02 dra72x scaling_governor not found
Part Number: TDA2E
Hi
I try to run omapconf show opp,but it show scaling_governor not found.
If I want to use this to chane frequency,what I need to set up?
thanks
Yumei
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AM5728: Can IVA-H264 encoder include Picture Timing SEI ?
Part Number: AM5728
Hi,
I want to include Picture Timing SEI in a H264 file encoded by IVA.
I can include SEI data but I think that is invalid data. I want to know the way to include Picture Timing SEI.
To include SEI data, I checked H264_Encoder_HDVICP2_UserGuide ( Appendix B ), and following code was added to gstducatih264enc.c.
params->nalUnitControlParams.naluControlPreset =
IH264_NALU_CONTROL_USERDEFINED;
params->nalUnitControlParams.naluPresentMaskStartOfSequence = 0x21A0;
params->nalUnitControlParams.naluPresentMaskIDRPicture = 0x21A0;
params->nalUnitControlParams.naluPresentMaskIntraPicture = 0x0002;
params->nalUnitControlParams.naluPresentMaskNonIntraPicture = 0x0002;
params->nalUnitControlParams.naluPresentMaskEndOfSequence = 0x0C00;
/* IDR frame includs SEI */
IH264ENC_SET_NALU(params->nalUnitControlParams.naluPresentMaskIDRPicture, SEI);gstreamer pipeline
gst-launch-1.0 -e \ v4l2src device=/dev/video1 num-buffers=2000 io-mode=4 ! \ 'video/x-raw,format=(string)YUY2,width=(int)1280,height=(int)720,framerate=(fraction)30/1' ! \ queue ! vpe num-input-buffers=8 ! 'video/x-raw,format=(string)NV12,width=(int)1280,height=(int)720' ! queue! \ ducatih264enc level=level-51 profile=high intra-interval=10 inter-interval=5 ! queue ! h264parse ! filesink location=test.h264
I parse the NALU in test.h264 using ffmpeg.
It seems that Picture Timing SEI exsists but SEI payload size is only one. So, I think it is invalid SEI data.
I want to know the way to include Picture Timing SEI.
My environment is,
board: AM5728 evm
SDK ver: 5.03
camera: mt9t11
Best Regard,
Reona
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Compiler/AM3352: DDR2 is hanging at Ramdisk in complete write and kernel panic
Part Number: AM3352
Tool/software: TI C/C++ Compiler
Dear all,
I am booting uImage, initrd.uboot(filesystem) and device tree using bootm command in DDR2 but device is hanging at filesystem execution with following errors.
[ 2.298980] RAMDISK: gzip image found at block 0
[ 2.481725] RAMDISK: incomplete write (20068 != 32768)
[ 2.487147] write error
[ 2.566938] VFS: Mounted root (ext2 filesystem) on device 1:0.
[ 2.573245] EXT2-fs (ram0): error: ext2_get_inode: unable to read inode bloc5
[ 2.583119] devtmpfs: error mounting -5
[ 2.587617] Freeing unused kernel memory: 344K (c080d000 - c0863000)
[ 2.594337] EXT2-fs (ram0): error: ext2_get_inode: unable to read inode bloc0
[ 2.604194] Starting init: /sbin/init exists but couldn't execute it (error )
[ 2.611882] EXT2-fs (ram0): error: ext2_get_inode: unable to read inode bloc1
[ 2.621727] Starting init: /etc/init exists but couldn't execute it (error -)
[ 2.629314] EXT2-fs (ram0): error: ext2_get_inode: unable to read inode bloc7
[ 2.639174] Starting init: /bin/init exists but couldn't execute it (error -)
[ 2.646760] EXT2-fs (ram0): error: ext2_get_inode: unable to read inode bloc7
[ 2.656611] Starting init: /bin/sh exists but couldn't execute it (error -5)
[ 2.663993] Kernel panic - not syncing: No working init found. Try passing .
[ 6029.08CC
But same filesystem is booting fully from NOR flash. When i boot from DDR2 using bootm command it is not booting.
Please let me know how to solve this issue with my custom AM3352 board.
Regards,
Subramanya N M
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TMS320DM8168: DM8168
Part Number: TMS320DM8168
Hi,
DDR3 of DM8168 processor is working at 1.5V level, Please let me know the logic (eg :CMOS, LVDS) of DDR3.
In the same way PCIe of DM8168 processor is also working at 1.5V level, Please let me know the logic (eg :CMOS,LVDS) of PCIe.
Regards,
Shyama
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Compiler/AM3358: UART3 configuration
Part Number: AM3358
Tool/software: TI C/C++ Compiler
Dear,
We are using AM3358 processor for development in that we have to interface UART3 module in UART mode. we also going to used CTS and RTS Pins for UART communication.
Please share us C code for UART3 configuration as soon as possible.
Thank you.
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TMS320C6678: AMI IBIS Init error in ADS tool
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TDA2E: vision SDK 3.02 dsp change OPP_NOM to OPP_HIGH
Part Number: TDA2E
Hi
I try to change dsp frequency from OPP_NOM to OPP_HIGH or OPP_OD.
I modify DRA7_CORE_OPP from OPP_NOM to OPP_HIGH in Clock.c file.(file from ti_components/os_tools/linux/u-boot/u-boot/arch/arm/include/asm/arch-omap5/Clock.c)
But I use omapconf show opp to check result,it still is OPP_NOM.
Do anything I miss when I want to change dsp freqency?
thanks
Yumei
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AM5746: RTOS Ethernet driver
Part Number: AM5746
Hi,
My customer encountered a data abort while evaluating Ethernet on a custom board.
(Test: "ping" frequently)
They reproduced this problem with TMDSIDK574.
(NIMU_BasicExample_idkAM574x_armExampleproject)
Test and workaround (Please visit the site to view this file)
Question 1:
Why is the variable type different depending on success or failure of EMAC_ALLOC_PKT()?
Question 2:
As a workaround, they changed the type of the failure's variable.
Is this workaround correct?
Regards,
Rei
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TMS320DM6437Q: Questions on TMS320DM6437Q
Part Number: TMS320DM6437Q
Hi Expert:
there are following questions on TMS320DM6437Q:
1. will it be discontinued? if so , is there alternative chip?
2.DSP main frequency is controlled by PLL1(SYSCLK1), is it possible to lower down PLL1 by divider through configure the register?if yes, how to configure it?which register is related,is it ?
| PLLDIV1 |
thanks.
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AM5728: PRU access from DSP
Part Number: AM5728
We want to use the PRU driver pdk_am57xx_1_0_12/packages/ti/drv/pruss/ from DSP1 in order to route to DSP1 data
preprocessed by one of the PRU. After having been processed by DSP1 the data will be further routed to a Linux application
running on the A15 core.
To do this we have started with the IPC example ipc_3_50_02_02\examples\DRA7XX_linux_elf\ex02_messageq.
The DSP1 executable is launched from Linux in the way explained at
software-dl.ti.com/.../Foundational_Components_IPC.html
However, as explained by the on-line messages reported below, the DSP1 software crashes
[ 107.635754] omap-rproc 40800000.dsp: assigned reserved memory node dsp1_cma@99000000
[ 107.643718] remoteproc remoteproc2: 40800000.dsp is available
[ 107.655344] remoteproc remoteproc2: powering up 40800000.dsp
...done
root@am5728-phycore-rdk:~# [ 107.662331] remoteproc remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 4006044
[ 107.679556] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[ 107.685455] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
[ 107.691400] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
[ 107.709538] virtio_rpmsg_bus virtio1: rpmsg host is online
[ 107.715062] omap-iommu 40d01000.mmu: iommu fault: da 0x4b2a6000 flags 0x0
[ 107.715070] remoteproc remoteproc2: crash detected in 40800000.dsp: type mmufault
[ 107.715081] omap-iommu 40d01000.mmu: 40d01000.mmu: errs:0x00000002 da:0x4b2a6000 pgd:0xedaed2c8 *pgd:px00000000
[ 107.739635] remoteproc remoteproc2: registered virtio1 (type 7)
[ 107.745584] remoteproc remoteproc2: remote processor 40800000.dsp is now up
If we understand it correctly, it is while accessing PRUSS2_CFG PRUSS_REVID register at address 0x4b2a6000 in the
function PRUICSS_create.
We have tried to solve the problem in creating a custom IPC resource table including a new TYPE_DEVMEM entry for the
PRU peripheral as explained in
processors.wiki.ti.com/.../IPC_Resource_customTable
but this did not solve the problem. We suppose that there is also something to do on the Linux side but, up to now, we
did not find what.
Could somebody please help us to solve this problem ?
Best regards,
Gilbert
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