Part Number:OMAP-L138
Hi,
I was asked by OMAP-L138 from my customer.
Please tell me about the read sequence of "20.2.5.6.6.2 4-Bit ECC" in the Technical Reference Manual.
1. What is the reason why the dummy lead of Step 10 was added by the revision of Rev. A -> Rev. B?
> 10. Perform a dummy read to any EMIFA registers except the
> NAND Flash error address 1-2 registers
> (NANDERRADD [2: 1]) or the NAND Flash error value 1-2
> Registers (NANDERRVAL [2: 1]).
Also, what will happen if we do not do this?
2. Is Step 10 necessary also when not carrying out the processing of Step 11 at this point?
3. If Step 10/11 is not executed, is the first NANDFSR read in Step 12 treated as a dummy read,
and the read value may become undefined?
(1 to 3 are returned to ECC_STATE although the calculation processing is not completed)
I am sorry that the question is difficult to understand.
I would appreciate it if you can answer.
Best Regards,
Miyashiro