How do I see DSP cache config registers in memory browser?

Hello,

From my DSP application code, I am writing to L2WWC (L2 Writeback Word Count Register Section) at address: 01844004h.  But when I look at this region in the memory browser (using CCSv6, and the XDS100v2 debug probe) I don't see this write taking effect.  How can I view the contents of the L1 and L2 configuration registers?   I can't find them in the Registers view in CCS either.

Also, something strange:  here is a line from Table 4-10. (L2 Cache Control Registers) in SPRUFK5A:

0184 4018h - L2IBAR - L2 Invalidate Base Address Register

And here is a line from Table 2-1. (L1P Cache Registers Summary) in the same doc:

0184 4020h L1PIBAR Level 1 Program Invalidate Base Address Register

It looks like overlapping registers.  They are both 32-bit registers, so wouldn't they overlap in memory by 2 bytes?

Thanks for any insights anyone can offer.

- Matt.