Part Number: OMAP-L137

Hello,

we have two products using OMAP L137. The first was released when this processor began its life when only the 375MHz version was available. We did power it at 1V2 core voltage (recommended nominal). We are currently using the DZKB3 silicon.

The second product uses the 456MHz version (DZKB4) and is powered at 1V3 core voltage (recommended nominal).

The question is, in order to have only one reference, can we safely use the 456MHz version (DZKB4) for our first product and power it at 1V2 voltage, knowing that the core frequency will not go beyond 375MHz ?

In other words, what causes the increase in nominal core voltage requirement : is it only due to higher max frequency operating condition, or the silicon is different for the 456MHz version ?

The Recommended Operating Conditions in the Datasheet gives 1V3 nominal and 1V25 min for the 456MHz version, so it seems that it's not a question of frequency but silicon.

Thank you,

Eric

Part Number: TDA2HG

On behave of customer.

We are using Vision SDK and Virtual DRM together. 

The VSDK version is 03.05.00.00. 

We porting QT to VSDK linux rootfs.

1. Vision SDK is to capture camera data and manage display.

2. GPU to do stitching and QT to draw the AVM diagram.

we met the problem as below.

PVR_K:(Error): SGXOSTimer() detected SGX lockup

Here is the full chart.

for the detail of the blue rectangle "VisionSDK" on the right-upper side, please see below chart.

we have done below tests:

1. remove VPE_sv_csc link, system not crash.

2. remove Capture_dsswb and Display_yuv422 link, system not crash.

Customer will try to test below case, then update to ticket.

3. comment AVM function, check if system crash.

log attached, 

(Please visit the site to view this file)

Would you please help check this problem and suggest next debug actions?

More information:

patch to use WB to output YUV422, see (Please visit the site to view this file)

Thanks a lot!

yong

Part Number: 66AK2G12

Hi

Is there any emulator available for 66AK2G12 device?

Regards

Srikanth Kacchu

Part Number: PROCESSOR-SDK-AM335X

Hello TI support community,

I am trying to modify (drivers/spi/spi-omap2-mcspi.c)
omap4 mcspi drivers in order to use interrupts instead of polling.
I use beaglebone black.
  After I set CS active and enable channel 0 and interrupts,
I receive only two interrupts (in fact a pair):
- tx0_empty and after this I fill the tx buffer by writing in the
mcspi tx reg n-times
and then reset the flag in IRQSTATUS
- as a follow up to the actions taken for tx0_empty,
rx0_full interrupt is risen and I read the mcspi rx reg n-times
and reset the flag in IRQSTATUS.
After that no interrupt comes (neither of tx_empty, rx_full or EOT)
even if interrupts and channel0 are enabled and CS is active,
so I can not transfer remaining data.
  FIFO is enabled and OMAP2_MCSPI_XFERLEVEL is setup accordingly (but similar happens if FIFO is disabled).
  Note that if I want to transfer a message that needs only one pair
of interrupts,
then EOT interrupt comes, which is the expected behavior.
  I used only transfer len less than DMA_MIN_BYTES (160) so dma is not used.
  If I use the polling method to see if something is pending on channel0
everything works well (this is the default behavior in spi-omap2-mcspi.c
omap2_mcspi_txrx_pio()).

Another thing: If I set CS active and enable channel 0, then in IRQSTATUS is set
up TX0_EMPTY and after interrupts are enabled, TX0_EMPTY interrupt will occur.
But if I reset the TX0_EMPTY bit in IRQSTATUS before enabling interrupts
(as the am335x manual says in chapter 24.3.4.1 Interrupt-driven operation:
The interrupt status bit should always be reset after the channel is
enabled and before the event is enabled as an interrupt source) then
no interrupts will occur even if I enable interrupts after that.

  Has anybody used omap4 mcspi in interrupt mode (without dma)?

Thank you and kind regards,
L-C. Duca

Part Number: AM5K2E02

Now we have DDR3 running on our custom board, I need to enable ECC and test that it is working.

The DDR3 starts at address 0x8000_0000

I have tried setting the ECC enable bit in the ECCCTRL register. i.e set value 0x8000_0000 at 0x2101_0110

My test has been to enable ECC, write a word in the DDR3 memory, then disable ECC and change one bit at that location.

I expect that after re-enabling ECC and trying to read the location, it should be corrected and ONE_BIT_ECC_ERR_CNT (0x2101_0130)  incremented.

I have also tried to follow the example ecc_test_app that is provided with the pdk_k2e_4_0_9 distribution to get an interrupt. According to the AM5K2E0x documentation, the DDR3_ERR interrupt is number 388. This doesn't match any of the interrupt numbers in the distribution.

Please can you help me find the correct settings.

thanks

Dan

Part Number: AM5728

Tool/software: TI C/C++ Compiler

Hai sir,

I am using AM5728 Evaluation board i am using below commands those are properly working but in c code those are not working.

1.Gst-launch-1.0 -v rtsp location="rtsp://admin:password@10.10.11.84:554" latency=0 ! rtpjitterbuffer ! rtph264depay ! h264parse ! ducatih264dec ! vpe ! videoconvert ! kmssink

2.Gst-launch-1.0 -v filesrc location=/home/root/video-samples/TearsofSteel-Short-720x420.h264 ! typefind ! h264parse ! ducatih264decvpe! kmssink

3. Gst-launch-1.0 playbin uri="rtsp://admin:password@10.10.11.84:554" latency=0 videosink=kmssink

above three properly working.

below code number 3 working 1&2 pipelnes not working

#include <gst/gst.h>
#include <stdio.h>

int main(int argc, char *argv[])
{
GstElement *pipeline;
GstBus *bus;
GstMessage *msg;

const gchar *nano_str;
guint major, minor, micro, nano;


/* Initialize GStreamer */
gst_init (&argc, &argv);

gst_version (&major, &minor, &micro, &nano);

printf ("GStreamer Version: %d.%d.%d\n",major, minor, micro);


/* Build the pipeline */
/*------1--------*/
//pipeline = gst_parse_launch("rtsp location=rtsp://admin:password@10.10.11.84:554 latency=0 ! rtpjitterbuffer ! rtph264depay ! h264parse ! ducatih264dec ! vpe ! videoconvert ! kmssink", NULL);

/*------2--------*/
//pipeline = gst_parse_launch("filesrc location=/home/root/video-samples/TearsofSteel-Short-720x420.h264 ! typefind ! h264parse ! ducatih264decvpe! kmssink", NULL);

/*------3--------*/
pipeline = gst_parse_launch("rtsp://admin:password@10.10.11.84:554 latency=0 videosink=kmssink", NULL);

/* Start playing */

gst_element_set_state (pipeline, GST_STATE_PLAYING);

/* Wait until error or EOS */
bus = gst_element_get_bus (pipeline);
msg = gst_bus_timed_pop_filtered (bus, GST_CLOCK_TIME_NONE, GST_MESSAGE_ERROR | GST_MESSAGE_EOS);

/* Free resources */
if (msg != NULL)
gst_message_unref (msg);
gst_object_unref (bus);
gst_element_set_state (pipeline, GST_STATE_NULL);
gst_object_unref (pipeline);
return 0;
}

This is how you could build it on the board in case your .c is named capture.c
gcc capture.c -o capture `pkg-config --libs --cflags gstreamer-1.0`

this is how to run it:
/etc/init.d/weston stop
./capture

1st and 2nd option not working only 3rd option is working

only displaying gstreamer-1.0 version showing no error

1st&2nd commented while required time un commenting and using

how to run the 1st and 2nd commands in c code

thanking you,

Ramachandra.PC

Part Number: AM5728

Tool/software: TI C/C++ Compiler

Hai sir,

I am using Beagleboard-X15 (AM5728) with Arago 2019.05 am57xx-evm SDK and i have some doubts.

1.while decoding AM5728 i am using Below commands(HIKVISION IP CAMERA (O/P:H264 Compressed video) to AM5728 Decoder Unit) and some frames are missing in decoder output where as camera output speed is 8Mbps through wireshark calculated around 6.5Mbps any changes to insert for in command for frames missing

HIKVISION camera:1920x1080(25fps)

a. sudo ifconfig eth1 10.10.11.85 netmask 255.255.254.0 up

b.export RTSP_PATH=rtsp://admin:password@10.10.11.84:554

c.Less delay(80ms) & less frmaes missing command: Gst-launch-1.0 -v rtsp location="$RTSP_PATH" latency=0 ! rtpjitterbuffer ! rtph264depay ! h264parse ! ducatih264dec ! vpe ! videoconvert ! kmssink

d.More delay(200ms) & More frmaes missing command: Gst-launch-1.0 -v rtsp location="$RTSP_PATH" latency=0 ! 'application/x-rtp, media=(string)video, clock-rate=(int)90000, encoding-name=(string)H264' ! rtpjitterbuffer ! rtph264depay ! h264parse ! ducatih264dec ! vpe ! 'video/x-raw, width=1920, height=1080, framerate=25/1, videoconvert ! kmssink

could you tell me any changes in command for less frame rate and i added queue also same thing showing

2..actually how to run program on power on only without any login and password of arago sdk (poweron how to run ./capture (/etc/init.d/)

Hi TI:

Some of our AM5718 main boards can't power up sometimes.

It will block on "start kernel".

MLO I/O re-calibration failed too.

Can you help to analyze root cause?

Thanks

Fail Log:
U-Boot SPL 2017.01-gf8adbe225f (Aug 28 2019 - 00:07:55)
DRA722-GP ES2.0
IODELAY: Isolation of Device IOs failed

Trying to boot from MMC2

U-Boot 2017.01-gf8adbe225f (Aug 28 2019 - 00:07:55 +0000)

CPU  : DRA722-GP ES2.0
Model: TI AM572x EVM Rev A3
Board: RV700
DRAM:  2 GiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1, OMAP SD/MMC: 2

Writing to MMC(1)... done
Writing to redundant MMC(1)... done

Hit any key to stop autoboot:  0
MMC: no card present
switch to partitions #0, OK
mmc1(part 0) is current device
active partition:
1
==>Load Kernel
391736 bytes read in 43 ms (8.7 MiB/s)
SD/MMC found on device 1
** File not found boot.scr **
** File not found uEnv.txt **
3973576 bytes read in 109 ms (34.8 MiB/s)
101626 bytes read in 14 ms (6.9 MiB/s)
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 8ffe4000, end 8ffffcf9 ... OK

Starting kernel ...

DarkHou

Part Number: TMS320C5517

Can anyone help me regarding the C5517 EVM? I have the evaluation board for this DSP and I am coding it using the CCS. I have also observed that the MMB0 board has a DSP and it is interfaced with the PC using a Labview. Can I find any documents that can be used so that I can interface the DSP with the PC using Labview? I want to acquire data from ADC using this DSP and put the data into the PC.  

• What does the ROV do, and how do I use it?
• Is there a difference between ROV and ROV Classic?
• Where can I find more training materials about the ROV?

Part Number: AM3358

hello every one

right now im try to build sdk using

and following this thread steps

this thread steps working fine for me but after this command

MACHINE=am335x-evm bitbake tisdk-rootfs-image

cpu usage goes to 100%

even after change in priority to very low priority from monitor

what should i do...?

it really metter ...?

it will damage my cpu...?

righ im using core i5 2400s cpu with 2.5Ghzx4 core and 12GiB of RAM and 8Gib of swap

Part Number: AM3358

hello

when i'm reading Sitara Linux Training: Getting Started with Openembedded

http://processors.wiki.ti.com/index.php/Sitara_Linux_Training:_Getting_Started_with_Openembedded

in this forum there is mansion you need 200GB of space if you want to build the full file system as shipped with Processor SDK Linux

does its really occupy 200GB of space in HDD ...?

Part Number: TDA3XEVM

Hello all,

I have an algorithm implemented in openCV and I want to import it on TDA3X EVM? . and can you also tell me also if TDA3X support importing algorithms from Tensor flow,

Thanks in advance

Part Number: TDA2PXEVM

Software version：ProcessRadarSdk 3.6

Can the radar_cascade_demo.m file be used in other use cases?E.g. radar_read_objectdetect_write usecase，Use networkTx output?

Hello,

I assume that PRU MII Tx_Overflow triggers when the FIFO is FULL and we try to push another byte into it.

Q1- So, Is the new byte overwrites the old one OR it's discarded?

Q2- So, Is the interrupt available at the next instruction cycle OR it takes some cycles?
I mean (I use C but Imagine at the next assembly instruction):

//suppose that FIFO is full and I try to push another byte
__R31 = 1<<24; //PUSH8

//is the Tx_overflow interrupt available in the next instruction i.e. below statement OR I must add some delay before checking??
if(CT_INTC.SECR1 & (1 << (52-32))) //check for tx1_overflow(event52) interrupt
{
    //Do something
} 

Q3- Is that correct that MII must send a frame data CONTINUOUSLY to phy? For example to send a packet larger than FIFO size e.g. 512 bytes, at no time in sending, FIFO can be empty, meaning that I can't send 64 bytes(make FIFO full) and then do some other things for a LONG TIME (FIFO is empty now) and then later come back and send the reset...
If that's the case, then we MUST poll Tx_overflow interrupt to see when we have room, then push another byte
Polling Tx_Underflow is not right here, meaning that put 64 bytes in fifo, waits for it to become empty and then put another 64 bytes and so on, since for a time herein the FIFO is empty and that contradicts with what I said above (CONTINUOUSLY sending frame data from mii to phy)

Q4- I try to send a packet larger than FIFO size e.g. 512 byte.
what is the problem in this code? because it doesn't work as expected and stucks in while when gpo is 92 i.e. sending 92th byte:
Tx1_overflow (event52) is mapped to channel0 and channel0 is mapped to host0
Tx1_overflow and host0 and global interrupt are enable ... I can see interrupt comes..

gpo = 0;
for (i=0; i<packetLength; i++)//send the pack start
{
    gpo++;
    __R30 = 0xFFFF0000 | gpo;
    __R31 = PUSH8;
    while(isSysEventPending(PORT1_TX_OVERFLOW_EVENT))
    {
        /Clear event and try again ... Persist on sending byte
        clearSysEvent(PORT1_TX_OVERFLOW_EVENT);
        __R31 = PUSH8;
    }
}
//i-PRU clk is 200MHz and MII clk is 25MHz -> pru clk = 8 * mii clk
//ii-MII sends 4 bits in each mii cycle since it has 4 lines Tx[3..0] -> one byte takes 2 mii cycle
//From i and ii, I can infere that sending a byte by MII takes 16 cycles of PRU clk
//Each byte takes 16cycles and we need 4 bytes empty for CRC -> 4bytes takes 64cycles ... some make pru to wait for 64 cycles to have 4 bytes room in FIFO for CRC
__delay_cycles(64);
__R31 = CRCLOW | CRCHIGH | EOF;



void clearSysEvent(uint32_t event)
{
    if(event >=0 && event <=31)
    {
        CT_INTC.SECR0 = 1 << event;
    }
    else //event 32 to 63
    {
        CT_INTC.SECR1 = 1 << (event-32);
    }

    return;
}


uint8_t isSysEventPending(uint32_t event)
{
    uint8_t isPending = 0;

    //Enabled Event
    if(event >=0 && event <=31)
    {
        isPending = (CT_INTC.SECR0 & (1 << event)) ? 1 : 0;
    }
    else //event 32 to 63
    {
        isPending = (CT_INTC.SECR1 & (1 << (event-32))) ? 1 : 0;
    }

    return isPending;
}

Q5- when do TX_Overflow and TX_Underflow interrupts trigger? and how do they treat?

Thanks for your help

Part Number: PROCESSOR-SDK-OMAPL138

We currently have products using the OMAP L138 processor, with the DSP core running SYS/BIOS and the ARM core running Linux.  We use IPC for these to communicate.  The Linux side uses SysLink to communicate with the DSP core, and in particular the SysLink "slaveloader" to load the firmware onto the DSP..  We're currently running with a 5-year-old version of Linux, Code Composer Studio, and SYS/BIOS.

I'd like to upgrade our build systems to something more modern.  I've downloaded the Processor SDK installers for Linux and TI-RTOS, as well as the latest CCS.  I'm now trying to get libraries in place so that I can start rebuilding our system.

When I went to download the IPC installer though, I saw a warning that IPC v3 is not compatible with SysLink.  No problems, I thought, so long as there's something to use instead.  When I looked at the IPC v3 docs though, it's worse than that - you've also removed the Notify and SharedRegion APIs.  The "Migration guide" (http://processors.wiki.ti.com/index.php/IPC_3.x_Migration_Guide) is spectacularly unhelpful - it tells me what has been removed, but contains not one single word on how to migrate to the new version.

In the absence of any documentation, please can you advise me on what should be used instead of SysLink "slaveloader", and what should be used instead of the Notify and SharedRegion features?  And more than just what to use, also where I can find information on how to use it to achieve the same functionality as I already have in IPC v1?

Part Number: TDA2SX

Dear TI,

I am working with TDA2SX custom board, the vision sdk revision i used is 3.6.

When i try to run the lvdsvipmulticam_sgxdisplay chains, i get the following error:

PVR_K:(Error): DmaBufImportAndAcquirePhysAddr: dma_buf_get failed: -22
PVR_K:(Error): PVRSRVMapDmaBufKM: Failed to get dma-buf phys addr
PVR_K:(Error): PVRSRVMapDmaBufBW: Failed to map dma-buf handle
EGL: after eglCreateImageKHR() eglError (0x3003)
ASSERT (system_gl_egl_utils.c|System_eglWindowGetTexYuv|803)
EGL: ERROR: eglCreateImageKHR failed !!!
EGL: ERROR: Unable to bind texture[1] to dmabuf fd [0] !!!

I do not know how to debugging this. 

The attached file is the kernel and app startup log.

(Please visit the site to view this file)

Regards,
Liu Gan

Part Number: TMS320C6678

Hello Champs,

Customer used mcsdk_2_01_02_06\demos\hua\src\benchmark to test the ethernet performance. Do we have Gigabit Ethernet throughput benchmark for TCP/UDP?

I found there is no NDK benchmark in NDK docs folder.

Thanks.
Rgds

Shine

Part Number: AM3358

Hi.

I'm using "SDK: ti-processor-sdk-linux-am335x-evm-06.01.00.08".
I consulted the SDK and while configuring Configure / Autotools, I met the following error:

http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Overview_Getting_Started_Guide.html

Part Number: PROCESSOR-SDK-TDAX

Hello,

while building sdk for TDA4 encountering some errors and errors are mentioned below

ERROR: external-arm-toolchain-2019.03-r0 do_install: Function failed: do_install (log file is located at /home/che7-l20149/TDA4/SDK/yocto-build/build/arago-tmp-external-arm-toolchain/work/aarch64-linux/external-arm-toolchain/2019.03-r0/temp/log.do_install.13534)
ERROR: Logfile of failure stored in: /home/che7-l20149/TDA4/SDK/yocto-build/build/arago-tmp-external-arm-toolchain/work/aarch64-linux/external-arm-toolchain/2019.03-r0/temp/log.do_install.13534

log.do_install.13534contain

DEBUG: Executing python function extend_recipe_sysroot
NOTE: Direct dependencies are ['/home/che7-l20149/TDA4/SDK/yocto-build/sources/oe-core/meta/recipes-devtools/quilt/quilt-native_0.65.bb:do_populate_sysroot', 'virtual:native:/home/che7-l20149/TDA4/SDK/yocto-build/sources/oe-core/meta/recipes-extended/xz/xz_5.2.4.bb:do_populate_sysroot', 'virtual:native:/home/che7-l20149/TDA4/SDK/yocto-build/sources/oe-core/meta/recipes-devtools/pkgconfig/pkgconfig_git.bb:do_populate_sysroot', 'virtual:native:/home/che7-l20149/TDA4/SDK/yocto-build/sources/oe-core/meta/recipes-devtools/bison/bison_3.0.4.bb:do_populate_sysroot', 'virtual:native:/home/che7-l20149/TDA4/SDK/yocto-build/sources/oe-core/meta/recipes-devtools/pseudo/pseudo_git.bb:do_populate_sysroot']
NOTE: Installed into sysroot: []
NOTE: Skipping as already exists in sysroot: ['quilt-native', 'xz-native', 'pkgconfig-native', 'bison-native', 'pseudo-native', 'automake-native', 'gnu-config-native', 'flex-native', 'libtool-native', 'autoconf-native', 'gettext-minimal-native', 'texinfo-dummy-native', 'm4-native']
DEBUG: Python function extend_recipe_sysroot finished
DEBUG: Executing shell function do_install
cp: cannot stat '../../../Toolchains/gcc-arm-8.3-2019.03-x86_64-aarch64-linux-gnu/aarch64-linux-gnu/lib64/*': No such file or directory
WARNING: exit code 1 from a shell command.
ERROR: Function failed: do_install (log file is located at /home/che7-l20149/TDA4/SDK/yocto-build/build/arago-tmp-external-arm-toolchain/work/aarch64-linux/external-arm-toolchain/2019.03-r0/temp/log.do_install.13534)

can anyone say what could be the reason?

thanks,

Akshatha