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TDA2HG: [TDA2HG] Displayout yuv422 over LVDS

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Part Number: TDA2HG

Hello:

SDK:

 VisionSDK 3.05

Display data flow :

QT-APP -->weston(RGB)-->VDRM -->dispaly_m4-->lvds(yuv422)

  •     displaytype
gChains_usecaseCfg.displayType = CHAINS_DISPLAY_TYPE_LCD_10_INCH;

    else if(displayType == CHAINS_DISPLAY_TYPE_LCD_10_INCH)
    {
        pPrm->deviceId = DISPLAYCTRL_LINK_USE_LCD;
        pVInfo->vencId = SYSTEM_DCTRL_DSS_VENC_LCD1;
        pVInfo->outputPort = SYSTEM_DCTRL_DSS_DPI1_OUTPUT;
        pVInfo->vencOutputInfo.vsPolarity    =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
        pVInfo->vencOutputInfo.hsPolarity    =   SYSTEM_DCTRL_POLARITY_ACT_LOW;

        /* Below are of dont care for EVM LCD */
        pVInfo->vencOutputInfo.fidPolarity      =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;
        pVInfo->vencOutputInfo.actVidPolarity   =   SYSTEM_DCTRL_POLARITY_ACT_HIGH;

        pVInfo->mInfo.standard                  =   SYSTEM_STD_CUSTOM;
        pVInfo->mInfo.width                     =   displayWidth;
        pVInfo->mInfo.height                    =   displayHeight;
        pVInfo->mInfo.scanFormat                =   SYSTEM_SF_PROGRESSIVE;
        pVInfo->mInfo.pixelClock                =   74500U;
        pVInfo->mInfo.fps                       =   60U;
        pVInfo->mInfo.hBackPorch                =   80U;
        pVInfo->mInfo.hSyncLen                  =   62U;
        pVInfo->mInfo.hFrontPorch               =   48U;
        pVInfo->mInfo.vBackPorch                =   12U;
        pVInfo->mInfo.vSyncLen                  =   35U;
        pVInfo->mInfo.vFrontPorch               =   6U;
        pVInfo->vencDivisorInfo.divisorLCD      =   1;
        pVInfo->vencDivisorInfo.divisorPCD      =   1;

        pVInfo->vencOutputInfo.dataFormat       =   SYSTEM_DF_RGB24_888;
        pVInfo->vencOutputInfo.dvoFormat        =
                                    SYSTEM_DCTRL_DVOFMT_GENERIC_DISCSYNC;
        pVInfo->vencOutputInfo.videoIfWidth     =   SYSTEM_VIFW_24BIT;

        pVInfo->vencOutputInfo.pixelClkPolarity =   SYSTEM_DCTRL_POLARITY_ACT_LOW;
        pVInfo->vencOutputInfo.aFmt             =   SYSTEM_DCTRL_A_OUTPUT_MAX;

        /* Configure overlay params */

        ovlyPrms->vencId                       = SYSTEM_DCTRL_DSS_VENC_LCD1;

  • vdrm in dts

      

                vdrm0: vdrm@0 {
                        compatible = "ti,dra7-vdrm";
                        vdrm0_crtc0: crtc@0 {
                                compatible = "ti,dra7-vdrm-crtc";
                                x-res = <1280>;
                                y-res = <720>;
                                refresh = <60>;
                                supported-formats = <DT_DRM_FORMAT_XRGB8888 DT_DRM_FORMAT_ARGB8888>;
                        };
                };

  sprintf((char *)pUcObj->DispDistSrc_westonPrm.vDrmControllerName,
          V_CONTROLLER_NAME);
  pUcObj->DispDistSrc_westonPrm.vDrmControllerObjectId = VDRM_CRTC;
  pUcObj->DispDistSrc_westonPrm.vDrmControllerObjectType =
      DISP_DIST_SRC_LINK_DRM_OBJECT_TYPE_CRTC;
  pUcObj->DispDistSrc_westonPrm.width = displayWidth;
  pUcObj->DispDistSrc_westonPrm.height = displayHeight;
  pUcObj->DispDistSrc_westonPrm.format = SYSTEM_DF_BGRX24_8888;

  DisplayLink_CreateParams *pPrm_display;

  pPrm_display = &pUcObj->Display_m4Prm;
  pPrm_display->rtParams.tarWidth = displayWidth;
  pPrm_display->rtParams.tarHeight = displayHeight;
  pPrm_display->rtParams.posX = 0;
  pPrm_display->rtParams.posY = 0;
  pPrm_display->displayId = DISPLAY_LINK_INST_DSS_VID1;
  ChainsCommon_SetDisplayPrms(&pUcObj->Display_m4Prm, NULL,
                              pObj->chainsCfg->displayType, displayWidth,
                              displayHeight);

and the document(PROCESSOR_SDK_VISION_03_07_00_00_Docs_Only/docs/TrainingSlides/Video_Drivers_Overview.pdf) say for video pipeline it can do color space conversion.

Question

  1. in this case, how we can directly output the RGB to yuv over LVDS
  2. or configure the weston output to yuv422
  3. Can we set pVInfo->vencOutputInfo.dataFormat = SYSTEM_DF_YUV422I_YUYV

Thanks.


Compiler/AM3359: Qt build error

Compiler/AM3359: Qt questions

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Part Number: AM3359

Tool/software: TI C/C++ Compiler

hello

im unable to fil=nd proper resources how to add qwt lib in qt setup and how to built qt chart or qwt lib for qt

bcoz in my qt say no module name "QtChart"

even after adding qt += gui chart

TDA4VMXEVM: How to access "QUAD-PORT ETHERNET EXPANSION BOARD" on Linux

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Part Number: TDA4VMXEVM

Hi,

We have successfully booted the Linux using the SD card and we were able to configure the single Ethernet Port available on the evaluation board (MCU GB ETHERNET).

However we want to write an application which will use the Ethernet ports available on the Ethernet Expansion Board.

What do we need to do to make those ports usable?

Can we use them on Linux or do we have to run RTOS on R5 cores to use those ports?

Best regards

Adam Kubiak

AM6548: DP display support

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Part Number: AM6548

there is a DP convert board along with the EVM, how to output display on this port?

root@am65xx-evm:~#
weston-simple-egl
weston-simple-egl: ../weston-2.0.0/clients/simple-egl.c:890: main: Assertion `display.display' failed.
Aborted (core dumped)
root@am65xx-evm:~# modetest
trying to open device 'i915'...failed
trying to open device 'amdgpu'...failed
trying to open device 'radeon'...failed
trying to open device 'nouveau'...failed
trying to open device 'vmwgfx'...failed
trying to open device 'omapdrm'...failed
trying to open device 'exynos'...failed
trying to open device 'tilcdc'...failed
trying to open device 'msm'...failed
trying to open device 'sti'...failed
trying to open device 'tegra'...failed
trying to open device 'imx-drm'...failed
trying to open device 'rockchip'...failed
trying to open device 'atmel-hlcdc'...failed
trying to open device 'fsl-dcu-drm'...failed
trying to open device 'vc4'...failed
trying to open device 'virtio_gpu'...failed
trying to open device 'mediatek'...failed
trying to open device 'meson'...failed
trying to open device 'pl111'...failed
no device found

DRA829 : questions on supply signals and naming

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Hi everybody , 

-->   what is the diference between  VDD_xxx e VDDAR_xxx   ?   I cannot find it in the manual 

--> what is “VDDS*_MCU”   ?  it is mentioned in TRM  pag 1705  but I cannot find in table 4-124 del DM

thank you 

best regards

Carlo

Compiler/TMS320C6654: About EDMA3 use on Keystone I

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Part Number: TMS320C6654

Tool/software: TI C/C++ Compiler

Hi,

I want to use DMA to transfer array data to NOR flash with SPI.

I want to confirm that my understanding is correct or not.

If the transferred data size is 512kByte, using AB sync transfer(ACNT = 65536(64kByte) * BCNT = 8) is fit within 1 frame. Is this correct ?

Or if the data array is type of float a[512][32][32], Is it correct to transfer as (ACNT = 4(4Byte) * BCNT = 65536 * CCNT = 2) ?

Also, in these case, I think that only one PaRAM set is needed as transfer the same data so it doesn't need linking. Is this correct ?

regards,

AM4376: Kernel warning

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Part Number: AM4376

Hi,

I browsed forum but cannot find exact response to my issues. IIRC L3 interconnect is not available so cannot really understand what is going on.

I have this in my bootlog:

NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor ladder
cpuidle: using governor menu
------------[ cut here ]------------
WARNING: CPU: 0 PID: 1 at /kernel-source//drivers/bus/omap_l3_noc.c:147 l3_interrupt_handler+0x2e0/0x344
44000000.ocp:L3 Custom Error: MASTER M2 (64-bit) TARGET GPMC (Read): Data Access in User mode during Debug access
Modules linked in:
CPU: 0 PID: 1 Comm: swapper Not tainted 4.12.28-wifi-emc-dut #6
Hardware name: Generic AM43 (Flattened Device Tree)
[<c010fa08>] (unwind_backtrace) from [<c010c45c>] (show_stack+0x20/0x24)
[<c010c45c>] (show_stack) from [<c04cc0d4>] (dump_stack+0x20/0x28)
[<c04cc0d4>] (dump_stack) from [<c01324ac>] (__warn+0xec/0x108)
[<c01324ac>] (__warn) from [<c0132510>] (warn_slowpath_fmt+0x48/0x50)
[<c0132510>] (warn_slowpath_fmt) from [<c04fe370>] (l3_interrupt_handler+0x2e0/0x344)
[<c04fe370>] (l3_interrupt_handler) from [<c0170fac>] (__handle_irq_event_percpu+0xd4/0x238)
[<c0170fac>] (__handle_irq_event_percpu) from [<c017113c>] (handle_irq_event_percpu+0x2c/0x68)
[<c017113c>] (handle_irq_event_percpu) from [<c01711e4>] (handle_irq_event+0x6c/0x90)
[<c01711e4>] (handle_irq_event) from [<c0174a9c>] (handle_fasteoi_irq+0xc4/0x164)
[<c0174a9c>] (handle_fasteoi_irq) from [<c01701d0>] (generic_handle_irq+0x28/0x38)
[<c01701d0>] (generic_handle_irq) from [<c0170838>] (__handle_domain_irq+0xc0/0xdc)
[<c0170838>] (__handle_domain_irq) from [<c0101544>] (gic_handle_irq+0x60/0x8c)
[<c0101544>] (gic_handle_irq) from [<c093108c>] (__irq_svc+0x6c/0xa8)
Exception stack(0xef11db58 to 0xef11dba0)
db40:                                                       ef1c3300 ef1f4b80
db60: 00000000 00000000 ef1f4b80 ef1c3300 00000000 00000000 00000015 ef1c3338
db80: 60000013 ef11dbdc ef11dba8 ef11dba8 c0172ddc c0172d18 60000013 ffffffff
[<c093108c>] (__irq_svc) from [<c0172d18>] (__setup_irq+0x548/0x66c)
[<c0172d18>] (__setup_irq) from [<c0172fbc>] (request_threaded_irq+0xc4/0x17c)
[<c0172fbc>] (request_threaded_irq) from [<c0175730>] (devm_request_threaded_irq+0x7c/0xb8)
[<c0175730>] (devm_request_threaded_irq) from [<c04fe508>] (omap_l3_probe+0x134/0x214)
[<c04fe508>] (omap_l3_probe) from [<c05d81fc>] (platform_drv_probe+0x60/0xac)
[<c05d81fc>] (platform_drv_probe) from [<c05d63d4>] (driver_probe_device+0x214/0x2dc)
[<c05d63d4>] (driver_probe_device) from [<c05d6644>] (__device_attach_driver+0xa4/0xbc)
[<c05d6644>] (__device_attach_driver) from [<c05d4700>] (bus_for_each_drv+0x98/0xa0)
[<c05d4700>] (bus_for_each_drv) from [<c05d6108>] (__device_attach+0xac/0x114)
[<c05d6108>] (__device_attach) from [<c05d6678>] (device_initial_probe+0x1c/0x20)
[<c05d6678>] (device_initial_probe) from [<c05d56a0>] (bus_probe_device+0x38/0x90)
[<c05d56a0>] (bus_probe_device) from [<c05d3880>] (device_add+0x414/0x514)
[<c05d3880>] (device_add) from [<c0729050>] (of_device_add+0x44/0x48)
[<c0729050>] (of_device_add) from [<c07295a8>] (of_platform_device_create_pdata+0x94/0xc4)
[<c07295a8>] (of_platform_device_create_pdata) from [<c0729680>] (of_platform_bus_create+0x84/0x1f8)
[<c0729680>] (of_platform_bus_create) from [<c072996c>] (of_platform_populate+0x84/0xd8)
[<c072996c>] (of_platform_populate) from [<c0e0fc24>] (pdata_quirks_init+0x68/0xa0)
[<c0e0fc24>] (pdata_quirks_init) from [<c0e0f70c>] (omap_generic_init+0x1c/0x28)
[<c0e0f70c>] (omap_generic_init) from [<c0e03ac4>] (customize_machine+0x2c/0x38)
[<c0e03ac4>] (customize_machine) from [<c0101bf0>] (do_one_initcall+0x134/0x15c)
[<c0101bf0>] (do_one_initcall) from [<c0e00f88>] (kernel_init_freeable+0x1d4/0x290)
[<c0e00f88>] (kernel_init_freeable) from [<c092b5e8>] (kernel_init+0x18/0x11c)
[<c092b5e8>] (kernel_init) from [<c0107b08>] (ret_from_fork+0x14/0x2c)
---[ end trace ca236957eef2cfb1 ]---
OMAP GPIO hardware version 0.1

So from above error message it seems that GPMC is trying to read something but in dts we have gpmc disabled (we don't use it we use eMMC and sdio). Is there any chance to get more insight what does this warning means (board normally boots and works just having warning in bootlog is not nice ;)).
Thanks,
marek


PROCESSOR-SDK-AM65X: TTS support

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Part Number: PROCESSOR-SDK-AM65X

Hi Team,

 

Timed Triggered SendTTS is supported by the icss_emac driver for AM3x/4x/5x.

The icss_emac driver for AM65x is integrated in EMAC (CPSW) driver.

It seems that TTS is not supported by EMAC (CPSW) driver.

Q1, Is my understanding correct?

Q2, If Q1 is yes, will it be supported in future releases?

Q3, If Q2 is yes, when will it be released?

 

Thanks and Best regards,

Kuerbis

AM4378: J23 on AM437x EVM

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Part Number: AM4378

I am reviewing the Am437x Evaluation Module schematic.  Page 23 of the schematic shows a J23 connection of reserved pins on the AM4378 processor.  What is this used for and should I put it in my design?

Thank you.

TMS320C6742: L1 cache configuration with AIS NOR boot

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Part Number: TMS320C6742

Hi,

We are developing an application for a C6742 DSP based production custom board and we are facing problems to fit our application code into the internal SRAM memory of this DSP.  We are launching our application by means of a AIS NOR boot, which configures by default the internal memories L1D, L1P as cache (32KB each) and L2 as RAM (64KB). In addition to these internal memories, our board features an external SDRAM memory connected through EMIF (with speed around 24MHz). 

During the application development we have been using the TMS320C6748 DSP Development Kit (LCDK), featuring the C6748 DSP, which has a greater L2 memory (256KB) than C6742. We have been running several tests allocating all the code into this augmented L2 memory, satisfying the time performance constraints defined for the application.

The problem is that our application code is far too big to be stored completely in the final L2 64KB SRAM memory of C6742 DSP (around 200KB), and we would want to minimize the code placed in the external SDRAM memory due to the time performace constraints I mentioned before. We have identified approximately the critical sections of the application code, on which those timing restrictions are mostly applied, and possibly they will not fil completely into L2 memory. So, assuming will need to take part of this code out of L2, we have considered two possibilities here:

- Place the most critical sections of the code in internal L2 memory and take the rest of it to the external SRAM memory. This will cause part of the critical code (not the most critical, but critical in some way) to be in a significantly slower memory, which possibly will affect the timing performance.

- Configure part of L1D, L1P memories as RAM so as to fit all critical code within internal memories (L1 and L2). The goal will be to maintain enough L1 memory space available for cache purposes to not slow down the coding execution but avoiding placing critical code in the external SRAM.

The second possibility could be the optimal, but raises several questions:

1. As far as I know, there are two possibilities to change the default configuration of L1 from cache to RAM: either instructing the bootloader to change that configuration or doing it in runtime in the code application itself. I do not know if the former way is possible for the AIS NOR boot, at least I did not see any reference to do that in the bootloader app note. I have seen some alternatives in similar threads on this topic such as a secondary bootloader, but I think this would mean to discard the AIS generation tool, am I wrong? On the other hand, I have seen an example of the runtime possibility in the Cache User Guide, section 2.7, but I do not know whether it is applicable to our case. In any case, I am wondering how tricky this be. Do you have any advise on that?

2. Considering the configuration can be done, what would be the criteria to allocate code to L1P and L1D memories? Is it enough to copy, for instance, .text sections (executable code)  to L1P and .far sections (static variables) to L1D, or other considerations should be taken into account?

3. I have seen in some GEL and .cmd files, and also in the datasheet documentation of C6724 that the L1P, L1D, L2 memories are often referred by two different addresses: [0x0080 0000, 0x00E0 0000, 0x00F0 0000] and [0x1180 0000, 0x11E0 0000, 0x11F0 0000]. The second group of addresses is referred as "shared" or "mirror". What is the difference between them? 

4. Would you have any estimation regarding to what extent the approach using L1 SRAM will offer a significative peformance gain respect to the one keeping the whole L1 as cache?

Any advise or help will be appreciated

Thanks,

David

WEBENCH® Tools/AM3352: SYS/BIOS: Calling BIOS_exit causes an assertion

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Part Number: AM3352

Tool/software: WEBENCH® Design Tools

I have an application that hits an assertion when it calls BIOS_exit(0), I'm using SYS/BIOS 6.73.1.1.  The error message that comes out is:  A_badContext: bad calling context. Must be called from a Task.  Googling a bit shows that this error will pop up when calling Semaphore_pend while not in a task.  Couple of questions:

- Is calling Semaphore_pend while not in a task the only time one gets a A_badContext error?

- Is there an API function that one can call to determine if they are in a task?

Interestingly, I have two other applications that have exactly the same code leading up to and into the call to BIOS_exit(0) that work just fine.  Unclear at present what is actually different with this one application compared with the other two.

Kevin Jennings

CCS/EVMK2G: request for detailed project bring up including LLD and debug tools

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Part Number: EVMK2G

Tool/software: Code Composer Studio

Hello,

Is there a detailed, step-by-step guide for creating a CCS project from scratch using the included tools and drivers in the SDK RTOS?

For instance, what I’m looking for is how to create the project for whatever processor, how and when to use the pinmux tool to define pin assignments, what to include (header files, struct initializations, etc.) for LLD support, how to create a project.cfg file, specifically what files have to be added to the project (right click, add files) vs #include, how to get more diagnostic tools working etc. 

Jorg

CCS/TI-PLC-G3-DC: Software Development request for concentrator design

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Part Number: TI-PLC-G3-DC

Tool/software: Code Composer Studio

Hello,
After my last request, in order to continue my light control project by plc, it would be possible to have access to the development kit TI-PLC-G3-DC for an example program.
Thank you for everything.

PROCESSOR-SDK-OMAPL138: Basic build issues

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Part Number: PROCESSOR-SDK-OMAPL138

Hi,

Some novice questions.

We're upgrading from mcsdk_1_01_00_02 to ti-processor-sdk-linux-omapl138-lcdk-06.00.00.07. and have been studying  docs/06_00_00_07/linux/Overview.html and related. We've downloaded and installed ...install.bin for RTOS and Linux. We've successfully built Linux and uBoot for LCDK  with defaults - OK. I would like to ask few basic questions to verify if we're on right path, HW is custom and has major differences to LCDK:

  • top level Makefile makes with 'tisdk_omapl138-lcdk_defconfig' and skips .config which we' ve just reconfigured - which is the right way to customize configuration
  • Which is recommended RFS, 'arago-base-tisdk-image-omapl138-lcdk'  or??
    • How can we forward 'install' there?
  • We need wpa_supplicant and gstreamer with related drivers, are they included in some of those filesystems or should we build and install them 'manually'?

We would like to minimize our effort to this upgrade as our resources are involved in application. Are there parties which could do this configuration with USD?

Best regards,

ristoH


AM4379: Verifying IEEE 1588 PTP Synchronization

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Part Number: AM4379

I have two demo boards: each with an AM4379 and an Ethernet interface. Both are running Linux and LinuxPTP.

I'm looking to run an experiment to verify the time synchronization between the two systems. Ideally, I'd like to toggle a GPIO at specific intervals on both cards and measure the time difference using an oscilloscope. However, I'm concerned about software jitter that may introduce delays in the measurements.

Is there some other suggested method for performing a test like this?

Thanks.

TDA2-17: Color 3D Model in GPU Based Surroundview

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Part Number: TDA2-17

Hello,

How do I enable a color 3D model using the TDA2xx EVM and the SGX based surroundview? All of the Car models are rendered as Grayscale despite having color texture files. 

Thanks

[DRA829]Question about DIO config in EB!!

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Hello,

DIO Port is several GPIO pins that are grouped by hardware.

1. I chenk datasheet again and focus on 14778 pages,seen on this page GPIO_BANK7_[0-15]    GPIO0_[112:127]; I think he means GPIO0_127 in GPIO0_B67_CH31 in DIO in EB tersos!!

But  In the Dio_cfg.h file I can't find the GPIO0_B67_CH31。 Why? 

Now I need use GPIO0_127 pin,How?

2.On 14778 page we can see GPIOn from BANK0_1[0-31] to BANK6_7[0-32] ,the two add up to a total of 127 pins , But in Dio_Cfg.h(line:181-189) we also can see GPIO0_B01-GPIO0_B45 total of 96 pins.

  32 pins missing!! Why?

3.On 14779 page we can see GPIOm only has BANK0_1[0-31] and BANK2[32-35] ,the two add up to a total of 36 pins  But in Dio_Cfg.h(line:181-189) we also can see GPIO1_B01-GPIO1_B45 total of 96 pins.  Why?

Thanks!!

Best wishes!

Linda Xie

AM6548: Motion JPEG codec

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Part Number: AM6548

Hi

Is the motion JPEG codec available on AM57x and also on AM65x at the point of HWA / SW liblary?

At AM57x,

  - IVA is available for motion JPEG enc/dec?

  - Is SW library for motion JPEG provided by Linux SDK?

At AM65x

  - Which HW accelerator is available for motion JPEG enc/dec?

  - Is SW library for motion JPEG provided by Linux SDK?

Thanks and Best regards,

HaTa.

AM5728: CMA address issue

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Part Number: AM5728


Hello Champs,

Hardware: combine 2x 16bit DDR3 to 32bit DDR
Software: Processor SDK 04.03.00.05

Customer reallocated CMA memory by modifying device tree and the related header file on dsp side. But some address can work, some address can't work, is there some limitation for the address range? 

When loading 2 dsp core at the first time, it can work, but when reloading the dsp code by using load-firmware.sh, it can't work at some address. The unwork DDR address can be read/written successfully with the memtester code. 

Below is the DTS:

/ {
compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";

aliases {
rtc0 = &mcp_rtc;
rtc1 = &tps659038_rtc;
rtc2 = &rtc;
display0 = &hdmi0;

sound0 = &hdmi;
sound1 = &sound0;
};

chosen {
stdout-path = &uart3;
};

memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};

reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

ipu2_cma_pool: ipu2_cma@b8000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xb8000000 0x0 0x2000000>;
reusable;
status = "okay";
};

dsp1_cma_pool: dsp1_cma@b0000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xb0000000 0x0 0x4000000>;
reusable;
status = "okay";
};

ipu1_cma_pool: ipu1_cma@ba000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xba000000 0x0 0x2000000>;
reusable;
status = "okay";
};

dsp2_cma_pool: dsp2_cma@b4000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xb4000000 0x0 0x4000000>;
reusable;
status = "okay";
};

dsp2dsp_shm: dsp2dsp_shm@bf000000 {
reg = <0x0 0xbf000000 0x0 0x1000000>;
no-map;
status = "okay";
};
};

Below is the memory map configuration on dsp side

#define CMA_DSP_PHYS_ADDR 0xb0000000
#define CMA_DSP_SIZE (SZ_1M * 56)
#define SR0_PHYS_ADDR 0xbf000000
#define SR0_SIZE (SZ_1M)
#define CMEM_PHYS_ADDR 0xbc000000
#define CMEM_SIZE (SZ_1M * 10)

//dsp cmd
#define DSP_MEM_TEXT 0xa0000000
#define DSP_MEM_DATA 0xa0200000
#define DSP_MEM_HEAP 0xa0400000
#define DSP_MEM_IPC_DATA 0xa0f00000
#define DSP_MEM_TEXT_SIZE (SZ_1M * 2)
#define DSP_MEM_DATA_SIZE (SZ_1M * 2)
#define DSP_MEM_HEAP_SIZE (SZ_1M * 3)
#define DSP_MEM_IPC_DATA_SIZE SZ_1M

//cmem
#define PHYS_MEM_IOBUFS CMEM_PHYS_ADDR
#define DSP_MEM_IOBUFS 0x80000000
#define DSP_MEM_IOBUFS_SIZE CMEM_SIZE

//SR0
#define PHYS_SR0 SR0_PHYS_ADDR
#define DSP_SR0 SR0_PHYS_ADDR
#define DSP_SR0_SIZE SR0_SIZE

/*
* Assign fixed RAM addresses to facilitate a fixed MMU table.
*/
/* Once you’ve created your custom resource table,
* you must update the address of PHYS_MEM_IPC_VRING
* to be the same base address as your corresponding CMA. */
#define PHYS_MEM_IPC_VRING CMA_DSP_PHYS_ADDR

#define DSP_MEM_IPC_VRING 0xc0000000
#define DSP_MEM_RPMSG_VRING0 0xc0000000
#define DSP_MEM_RPMSG_VRING1 0xc0004000
#define DSP_MEM_VRING_BUFS0 0xc0040000
#define DSP_MEM_VRING_BUFS1 0xc0080000

#define DSP_MEM_IPC_VRING_SIZE SZ_1M

/*
* Sizes of the virtqueues (expressed in number of buffers supported,
* and must be power of 2)
*/
#define DSP_RPMSG_VQ0_SIZE 256
#define DSP_RPMSG_VQ1_SIZE 256

/* flip up bits whose indices represent features we support */
#define RPMSG_DSP_C0_FEATURES 1

The DSP CMA address:

DSP1:0xb0000000~0xb3ffffff

DSP2:0xb4000000~0xb7ffffff

Reloading the dsp code,run the command: echo 40800000.dsp > /sys/bus/platform/drivers/omap-rproc/unbind, the system ran with below errors.

[ 457.348466] Unable to handle kernel paging request at virtual address f226608c
[ 457.355723] pgd = cf8d7b80
[ 457.358442] [f226608c] *pgd=80000080007003, *pmd=ac1f7003, *pte=00000000
[ 457.365200] Internal error: Oops: a07 [#1] PREEMPT SMP ARM
[ 457.365206] Modules linked in: cmemk(O)
[ 457.365213] CPU: 0 PID: 249 Comm: load-firmware.s Tainted: G O 4.9.65-rt23 #3

However, when modifying the DSP CMA address as follows. 

DSP1:0xa0000000~0xa3ffffff

DSP2:0xa4000000~0xa7ffffff

It can work successfully. 

Thanks.
Rgds
Shine

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