Part Number: 66AK2H12
Tool/software: Code Composer Studio
Hello All,
From the post 
i have a question.
"About the actions to take inside the ISR to clear the interrupt:
CpIntc_clearSysInt(0, System_event);
... //ISR custom action
Nothing to handle
//ISR custom action
Is this true for this cases? Should I clear the correponding flag or SYS/BIOS handles it in HWI?
Best Regars,
Kaan
Part Number: TMS320C6748
Hi,
I am trying to create an GUI Composer application for my DSP application. I was trying to work on GUI Composer v2. I could not find the target programming for TMS320C6748. I would be grateful if anyone could help. I am working on code composer v9.
Anup
Part Number: AM6548
Team,
The current Linux SDK only supports OpenGL ES 2.0. Will we be able to support OpenGL ES 3.0 in future?
Looks like this is due to HW limitations not possible on AM57x, but what about AM6x?
Thanks,
Robert
Part Number: BEAGLEBOARD-X15
TI/Beagleboard lists three distributors for ordering the Beagleboard X-15:
My question is: From the above, it appears the X-15 is either "lifecycle obsolete" or near the end of its lifecycle. Is that true? If so, then what will be replacing it?
(At the TI Tech Day, the sales people at Critical Link said they are developing an evaluation board for the AM572x, and it should be available in about 3 to 6 months. Is that true?)
-- Walter Snafu
Part Number: PROCESSOR-SDK-AM437X
We have run out of pins and are planning on setting up 3 wire UART1 with data enable on a gpio pin. I seem to remember reading forum articles that talked about supporting this, but I am not finding them now. Can anyone tell me if this is going to work and point me to some documentation?
james
Part Number: TMS320C6727
Hi, I'm running into what looks like a low-level or hardware issue which causes one of my functions to jump to a bogus address on return.
I'm using CCSV7 on linux and compiler 7.3.17. The function causing the issue is written in C. All assembly shown here is generated by the compiler.
The info from the assembly listing file for this function is:
;* FUNCTION NAME: xxxxxxxxxxxxxxxxxxxx *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14, *
;* A15,B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12, *
;* B13,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24,A25, *
;* A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20,B21, *
;* B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14, *
;* A15,B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,B12, *
;* B13,DP,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24, *
;* A25,A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20, *
;* B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
;* Local Frame Size : 0 Args + 40 Auto + 44 Save = 84 byte *When the function starts, the return address register B3 holds the correct return address 0x8046.FA9C.
The code is going to save B3 onto the stack at SP[20]; SP[20] is highlighted in the memory browser tab:
Everything looks as expected as the STW is about to be executed:
But SP[20] remains unchanged after the STW (B3 has changed per the other instructions):
Jumping to the end of the function, B3 is about to be loaded from the stack:
But the stack holds a bogus address, so the function does not return to the correct address.
If I manually set SP[20] to the correct value of 0x8046.FA9C when PC is at 0x8046.ECE0 then the function returns correctly and the rest of the code runs as expected. This is the only function in the entire program that shows this weird behavior.
As far as I can tell, the assembly code looks correct, assuming the code in the disassembly view is what the DSP is actually seeing.
It appears as if the hardware just does not perform the STW to SP[20]. I have also tried clearing SP[20] to 0 prior to executing the STW and it remains at 0, adding support to the theory that the STW is not executing.
Some more background: immediately prior to calling this function, we load some data out of flash memory via the async EMIF interface at 0x9000.0000 and save it to external RAM at 0x8000.0000. Part of the flash reading operation requires playing with some GPIOs on the UHPI interface to set the upper address bits for the flash chip. No interrupts are running at this point in the code.
Any ideas as to what could be causing this issue or how to resolve it? Thanks in advance.
Part Number: TMDXIDK5718
Hello,
Have you experienced with ping error on TMDXIDK5718?
In spite of the direct connection between PC and TMDXIDK5718 with Ethernet cable, some packets seem to be lost.
However, because this is very rare case (once per million and random), so we cannot find the cause.
SDK version : PROCESSOR-SDK-LINUX-RT-AM57X 06_00_00_07
EVM : TMDXIDK5718
direct connected PC (sending ping to EVM) : Ubuntu 18.04.2
Best Regards,
Nomo
Part Number: AM3505
I wanted to use your design resource to find all recommended PMICs that support the AM3505 Sitara Processor - using the following url:
When I click on the "Family" selection menu - there is no option to select the AM3505 SItara device.
I have also searched around the TI website looking for recommended PMICs for the AM3505 - with no luck.
Please supply a list of recommended PMICs for the AM3505 or show me where I can locate this information.
Thanks.
Part Number: DRA787
We are develop the log system link vision sdk log system,
We config a share memory use keyword CachePolicy_NON_CACHEABLE.
When we save log and log length to share memory in DSP1, the IPU1_0 get the log length , but the length is 0.
If save log length to share memory, then call CacheP_wbInv(), then IPU1_0 get the log length is correct.
It seems the share memory is cacheable,.
How to config non-cache share memory?
Part Number: DRA726
Is it possible to have communication between a Linux Kernel module and a Cortex M4?
Michel Catudal
Part Number: OMAP-L138
Tool/software: Code Composer Studio
Hi,
I run dsp library FFT code to see test time with 128 point 256 point and 512 point. The result is ok ,but test time are some abnormal .
256 point test time is nearly same with 128 point .I run on release mode on CCS 7.3 .
I use the FFT linear assemble function DSP_fft16x16 () form dsplib_c64Px_3_4_0_0\packages\ti\dsplib\src\DSP_fft16x16\c64P\DSP_fft16x16_sa.sa
The DSP_fft16x16 () test time of 128 points and 256 point is about 4us.but 512 point use about 6us.
I wonder why 128 point have same test time with 256 point ? Ara there some rules or setting about FFT point when run FFT function?
I use omap-L138 for my custom board ,but for now only use the dsp core.
Best Regards
Jacky
Hi.
Doesn't a tda4x have any color conversion module from YUV to RGB or another YUV format?
In TRM, it looks like the tda4x has a module for color conversion only from RGB444(12-bit) to YUV444(12-bit).
Best regards
Yongsig.
Part Number: AM4372
Sitara support team,
I would like to make sure that the following NOR Flash Memory can use a qspi boot for AM4376.
MICRON: MT25QL512ABB1EW9-0SIT
I have checked Section 5.2.6.7.1.in AM437x TRM and there is described...
-The boot device must default to quad mode, if quad-read support is desired
However MT25QL512ABB1EW9-0SIT is set "Quad I/O protocol" bit in Nonvolatile Configuration Register is "1 = Disabled (Default)".
Is this problem for using the NOR Flash Memory? Or is it not problem to use if "Quad I/O protocol" bit is set "0 = enabled"?
If there are any other limitations to use the NOR Flash Memory, please let me know.
Best regards,
Kanae
Part Number: TDA2SX
Hi All
I am Working on TDA2XX custom board.
I am facing issue with audio clock generation with help of BCLK.
my requirement is "I2S run on 48KHz sample rate stereo 24bits format, that is BCLK should be 3.072MHz"
I am using below devicetree to generate the clock
sound0: sound0 {
compatible = "simple-audio-card";
status = "okay";
simple-audio-card,name = "CS48L32";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line Out",
"Microphone", "Mic Jack",
"Line", "Line In";
/*
simple-audio-card,routing =
"ASP TX1 Source", "ASPTX1",
"ASP TX3 Source", "ASPTX3",
"ASPRX1", "VPMON ADC",
"ASPRX1", "VBSTMON ADC",
"AMP Playback", "ASPRX1",
"Main AMP", "SPK",
"CLASS H", "PCM Source"; */
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,mclk-fs = <256>;
sound0_master: simple-audio-card,cpu {
sound-dai = <&mcasp2>;
system-clock-frequency = <3072000>;
};
simple-audio-card,codec {
sound-dai = <&cs35l41_l>
};
};
But, audio is not working and with help fo aplay -vvv .wav file,it's playing very fast.
Can you please help me,where i am wrong ?
Thanks & Regards,
Sankar.
Part Number: AM5726
Tool/software: TI C/C++ Compiler
Hello
We want to test 16bit image sensor with am5726 Custom board, For that first, we want to do POC on the EVM.
Does AM5726 EVM support 16 bit sensor? If we purchase EVM then, Which camera sensor we need to order with it?
Regards,
Prerak
Hi,
my question is one can controller only can be configuration 64 hardwareobject in EB, But we now use more than 64 hardwareobjects on one can controller!!
How to solve this problem?
Thanks！
Best wishes!
Part Number: TMDX654IDKEVM
Hi,
I'm somewhat confused on the topic of UART Boot Mode. Does the UART Boot Mode support actual booting from an external memory (usb stick) ?
Thanks,
Part Number: AM3358
Hi,
As per the beaglebone reference manual, the default boot sequence is eMMC uSD UART0 USB0. In our application the required boot sequence is uSD eMMC UART0 USB0.
So do i need to connect MMC1 line to uSD for making uSD as primary source for boot memory? or is there any other settings.
Regards,
Hareesh.
Part Number: TMS320DM368
Tool/software: TI C/C++ Compiler
Hi Sir,
The TMS320DM368 uboot Just started to use the boot is no problem, to the client for a period of time there is a probability that the system can't be successfully started u-boot, the following figure is the error message, TI EVM has recommended to use Micron NAND Flash (We have used MT29F2G08AABWP), there are any suggested ways to improve?
Thank you!
Part Number: TDA2SX
Dear TI,
I am working on our tda2sx custom board with visionsdk verison 3.06 and the related release linux kernel version 4.4.84.
I was tring to make the ethernet interface working fine these days. But it seems that the mac controller cannot detect the phy chip.
dmesg info:
dts node decompiled from my dtb file:
ethernet@48484000 {
compatible = "ti,dra7-cpsw", "ti,cpsw";
ti,hwmods = "gmac";
clocks = <0x11b 0x11c>;
clock-names = "fck", "cpts";
cpdma_channels = <0x8>;
ale_entries = <0x400>;
bd_ram_size = <0x2000>;
mac_control = <0x20>;
slaves = <0x1>;
active_slave = <0x0>;
cpts_clock_mult = <0x784cfe14>;
cpts_clock_shift = <0x1d>;
reg = <0x48484000 0x1000 0x48485200 0x2e00>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ti,no-idle;
interrupts = <0x0 0x14e 0x4 0x0 0x14f 0x4 0x0 0x150 0x4 0x0 0x151 0x4>;
ranges;
syscon = <0x8>;
status = "okay";
dual_emac;
mdio@48485000 {
compatible = "ti,cpsw-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
ti,hwmods = "davinci_mdio";
bus_freq = <0xf4240>;
reg = <0x48485000 0x100>;
linux,phandle = <0x11d>;
phandle = <0x11d>;
};
slave@48480200 {
mac-address = [00 00 00 00 00 00];
phy_id = <0x11d 0x0>;
phy-mode = "rgmii";
dual_emac_res_vlan = <0x1>;
};
slave@48480300 {
mac-address = [00 00 00 00 00 00];
phy_id = <0x11d 0x3>;
phy-mode = "rgmii";
dual_emac_res_vlan = <0x2>;
status = "disabled";
ti,no-idle;
ti,no-reset-on-init;
};
cpsw-phy-sel@4a002554 {
compatible = "ti,dra7xx-cpsw-phy-sel";
reg = <0x4a002554 0x4>;
reg-names = "gmii-sel";
};
};
The following picture is the phy schematic.
I got two questions here.
1. The ifconfig command list three ports(eth0, eth1, lo), while i have disabled the cpsw_emac1 in the dts file. As we have only gmac_sw0 used in our board, how should i disalble the eth1 interface?
2. What should i do to make the eth0 interface working fine?
Another fact is that if i conect the board to my pc. I can get the connection information from the windows side as follow.
In my opinion, this may say that the phy chip is working, but the mac layer cannot make communication with it.
I am very new to linux kernel development. Hope for your reply.
Regards,
Liu Gan