Part Number: AM5728
Hello,
We are working on a custom board carrying AM5728 SOM Module from Phytec with following setup,
- Board carries Xilinx Artix-7 connected over PCIe bus (containing FPGA endpoint) to the SOM module
- ARM on AM5728 is used to load DSP firmware using remoteproc method
- DSP firmware running SYS/BIOS enumerates the endpoint using the provided PCIe libraries
On the software front,
- Linux 4.9.41 used is for booting is from Phytec GIT-repo
- This (pcie root-complex 1) is used on the DSP core for communication with endpoint implemented in FPGA
- PCIe RC is driven using external clock and PCIE RefClock register is programmed appropriately to select external clock
- DSP enumerates FPGA as a PCIe endpoint during firmware initialization
Application description,
- FPGA keeps providing interrupts once every ~2ms
- Upon receiving the interrupt, DSP starts EDMA transfer to fetch data from FPGA Fifo to DSP buffer (which is aligned to 256 bytes)
- DSP is required to process the received buffer and transmit back to a separate FPGA Transmit Fifo, again using EDMA, over PCIe bus
- It is possible for Transmit EDMA transfer to be active along with FPGA raising Rx interrupt at the same time
Issues being faced,
1. When both Transmit and Receive paths are enabled together, then, DSP PCIe driver is missing some Rx interrupts being raised by FPGA
2. Our FPGA engineer says that all raised interrupts are being acknowledged by a bus grant on PCIe bus. We have implemented an exception in case interrupt is raised by FPGA and bus grant is not received from PCIe root-complex, and this is never triggered during data transfers when check on FPGA ILA
3. When interrupts are missed, we are observing the ISR does not get invoked, even though the bus grant has been received by FPGA
4. From the DSP side, we keep profiling the duration between consecutive interrupts and flag off when duration is greater than 3ms
5. When Transmit path is disabled in our code, no Receive interrupts are missed in this condition
Any inputs on solving the missing interrupts issue will be appreciated. PLease let me know if any more information is needed.
thanks--
Somesh
