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PROCESSOR-SDK-AM335X: Kernel build fails

August 15, 2019, 1:19 am
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Part Number: PROCESSOR-SDK-AM335X

I got the SDK from TI. I have setup env and cross compiler. 

linux kernel version is "linux-4.9.69+gitAUTOINC+9ce43c71ae-g9ce43c71ae"

for the config, I use "make tisdk_am335x-evm_defconfig" and "make" .

fail information is

GEN     lib/oid_registry_data.c

/home/newrt/share/PDT/linux-devkit/sysroots/x86_64-arago-linux/usr/bin/perl: line 4: /home/newrt/share/PDT/linux-devkit/sysroots/x86_64-arago-linux/usr/bin/perl.real: No such file or directory

I am sure the file in path "/home/newrt/share/PDT/linux-devkit/sysroots/x86_64-arago-linux/usr/bin/perl.real" 

I am sure the compiler can access to this file

how should I fix this problem?

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TMS320C6748: There happens the failure of Vector.push_back.

August 15, 2019, 1:19 am
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Part Number: TMS320C6748

Dears:

There happens the failure of Vector.push_back, pls. refer the below picture:

Btw: There will happen the issue using DSP/BIOS, if not using BIOS the program(C++ Add STL) is OK.

compiler： TIC6000 V7.4.4

CPU: TMS320C6748

Tool：CCS5.5

Dsp/bios: 5.4.2

File format: COFF

The begin pointer: 0x00000000

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CCS/AM3358: Profibus Master issue

August 15, 2019, 1:42 am
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Part Number: AM3358

Tool/software: Code Composer Studio

Hello,

I want to boot my am3358-based platform with profibus master application from SD card. I want to know what should I do step by step to in order to run application in details? 

I created SD card image of TI-RTOS SDK and I copied prebuilt binary file of profibus master application (app) into my SD card. When I inserted SD card in my board, booting procedure failed and stopped. 

Thanks for your attention.

 

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AM5706: Power sequencing

August 15, 2019, 1:50 am
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Part Number: AM5706

     I want to use two TPS65261 cascades to power the AM5706. the VDDSHV_1 to VDDSHV_11  are all 3.3V.The power-up sequence I want to achieve is VDDS_1V8-----VDA_PLL_1V8----VDD_DDR_1V35 -----VDD_CORE_AVS-----VDD_DSP_AVS---VDA_PHY_1V8-----VIO_3V3---ddr1_vref0(VTT_DDR)---H_PORz。

      therefore， VIO_3V3  which is  used to power  VDDSHV1~VDDSH11(including VDDSH8) is the last power for AM5706。And it is used to generate DDR1_VREF and  H_PORz. So i think the VDDR_VREFSTL（ddr1_vref0） is  too later away from VDDS_DDR1?  From the power up  sequence pic，ddr1_vref0 and VDD_DDR_1V35 should be in front of VDD_DSP_AVS and other power，but from the note below，it says  it just must be valid before porz rising ,not mention the relationship between ddr1_vref0 and VDD_DSP_AVS.

Besides  I Even doubt it（ddr1_vref0）may after(behind）H_PORz. Is my idea correct? Is there any good advice about this ddr1_vref0 power supply?  

       As you see  pic below ，Equivalent to putting ddr1_vref0 behind vddshv8 (3.3V, merged with other VDDSHX)。

       (Please visit the site to view this file)

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[DRA829] JTAG - TDI and TCK pin needs to be connected with external Pull up ?

August 15, 2019, 2:22 am
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Support team.

I would like to confirm you about TDI/TCK pins of DRA829.

So, it needs to be connected with external pull up.

Br

KORO

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[DRA829] JTAG - TRSNn pin

August 15, 2019, 2:25 am
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Support team.

I would like to confirm you about TRSTn.

So, I would like to confirm if TRSn pin needs to be connected external pullup or pulldonw.

I believe that it needs to be connected with external pull down.

But I want to confirm you.

Br

KORO

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[DRA829] DDR0_RESETn signal

August 15, 2019, 2:37 am
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Hello Support team.

I would like to know about DDR0_RESETn signal.

I though that it may be connected with external Pulldown.

However, it is connected with external pullup from schematic of SOM.

I would like to get your advise.

DDR0_RESETn needs to be connected with pullup ?

Best Regards

KORO

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AM3352: Processor SDK image usage NAND boot

August 15, 2019, 2:38 am
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Part Number: AM3352

With latest Processor SDK 6.0 or 5.3:

#1. When to use MLO-am335x-evm or u-boot-spl.bin-am335x-evm?

#2. What is u-bot-spl-os and what is u-boot-env? where are those files?

#3. I want to use NAND boot, how to set UBOOT bootcmd and bootargs?

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Compiler/TIDEP-01002: early boot vision_sdk , sometimes iva not woring after kernel start

August 15, 2019, 2:40 am
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Part Number: TIDEP-01002

Tool/software: TI C/C++ Compiler

Hi Experts,

Recently I am doing the task about early boot with vision_sdk 3.04, kernel 4.4 and uboot 2016.05 on j6p.

I have already enable iva in uboot and not power on it in kernel. after doing this most of the time it runs ok.  but sometimes after entering kernel the iva will not work, and video freeze.

after checking the register i found the difference is(ok -->nok):

| CM_IVA_IVA_CLKCTRL    | 0x4A008F20   | 0x00040001 | ------> | CM_IVA_IVA_CLKCTRL    | 0x4A008F20   | 0x00000001 | 

So my question is what operation will cause the register value change, and how to debug the iva subsystem. 

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AM3352: USB_DRVVBUS problem

August 15, 2019, 3:15 am
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Part Number: AM3352

Hi TI team,
I'm tesing sleep mode on AM335x Starter Kit using the prebuilt image of Linux SDK 05_03_00_07.
After AM335x awake, there is no power on USB1_VBUS.
The voltage of USB1_DRVVBUS is zero .

How to fix the problem?


Log--------------------------------------------------------------------
root@am335x-evm:~# cat /sys/kernel/debug/musb-hdrc.1/softconnect
1
root@am335x-evm:~# echo mem > /sys/power/state
[ 123.248529] PM: suspend entry (deep)
[ 123.252180] PM: Syncing filesystems ... done.
[ 123.353627] Freezing user space processes ... (elapsed 0.003 seconds) done.
[ 123.364421] OOM killer disabled.
[ 123.368105] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
[ 123.378206] Suspending console(s) (use no_console_suspend to debug)
[ 123.538720] pm33xx pm33xx: PM: Successfully put all powerdomains to target state
[ 123.538720] PM: Wakeup source UART
[ 123.564360] net eth0: initializing cpsw version 1.12 (0)
[ 123.668587] Atheros 8031 ethernet 4a101000.mdio:00: attached PHY driver [Atheros 8031 ethernet] (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
[ 123.672721] net eth1: initializing cpsw version 1.12 (0)
[ 123.768712] Atheros 8031 ethernet 4a101000.mdio:01: attached PHY driver [Atheros 8031 ethernet] (mii_bus:phy_addr=4a101000.mdio:01, irq=POLL)
[ 123.957966] OOM killer enabled.
[ 123.961128] Restarting tasks ... done.
[ 124.037292] PM: suspend exit
root@am335x-evm:~# cat /sys/kernel/debug/musb-hdrc.1/softconnect
0
root@am335x-evm:~#

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[DRA829] if RESETSTATz pin can be used for module reset signal

August 15, 2019, 3:19 am
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Hello Support team.

The external IP/modules via eMMC, Ethernet, MIPI DSI and so on needs to be reset when system reset/power on.
I think it may be able to use "RESETSTATz" signal. But if this signal is asserted by only WarmReset, it cannot be used. In this case, GPIO signal needs to be used.
I would like to know if RESETSTATz can be used for external module reset.

Br

KORO

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AM3354: USB consistency test

August 15, 2019, 3:30 am
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Part Number: AM3354

dear sir

   l use the am3354BZCZD80, I want to do test the usb consistency of am3354, do you have test method or usb test instruction ? thanks you very much!

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[DRA829] PMIC_PWR_EN1 signal

August 15, 2019, 3:30 am
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Hello Support team.

I read "CTRLMMR_WKUP_MAIN_PWR_CTRL" discription in TRM.
Then PWR_EN explanation mentioned "PMIC_PWR_EN1". I believe that this signal is internal signal. However, I did not find this signal in DM/TRM.
I would like to know where this signal.

Br

KORO

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[DRA829] USB related pin

August 15, 2019, 4:11 am
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Support team.

I have some question for USB pins.
(1) I would like to know if USB0_ID and USB1_ID can be N/C(Open) when it will not be used.

(2) I would like to know if USB0_VBUS and USB1_VBUS can be connected with 3.3V when it will not be used.

(3) I would like to know if USB0_RCALIB and USB1_RCALIB needs to connect to PD (500Ω±１％） when it will not be used too.

(4) I would like to know If USB0_DM/DP and USB1_DP/DM can be N/A (Open) when it will not be used.

Best Regards

KORO

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[DRA829] - UFS0 related pins

August 15, 2019, 4:14 am
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Support team.

I have some question for UFS0.

(1) I would like to know if output signals of USF0 can be N/A (Open) when system does not use UFS0.
    In this case, I would like to know if UFS0_RX_DNx (Input signals) can be N/A(Open) too.

(2) DRA829_SR1.0_DM_vC.pdf mentioned that IO voltage of UFS0_RSTn and UFS0_CLK are 1.2V. Is this description correct ?
Best Regards
KORO
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[DRA829] - Serdes pins

August 15, 2019, 4:16 am
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Support Team.

I have question related SerDes.

I would like to know if unused pins of SerDes can be N/A (Open). 

Br

KORO

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[DRA829] - CSI1 pins

August 15, 2019, 4:17 am
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Support Team.

I have question related CSI1

(1) I would like to know if unused pins of CSI1 can be N/A (Open) when CSI1 will not be used.
(2) I would like to know if the PD resister (500Ω±１％) of CSI1_RXRCALIB can be removed when CSI1 will not be used.

Br

KORO

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[DRA829] PCIe pins

August 15, 2019, 4:18 am
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Support Team.

I have question related PCIe.

I would like to know if unused input pins of PCIE_RFECLK cab be N/A (Open).

Br

KORO

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[DRA829] - RESET_REQz and MCU_RESETz

August 15, 2019, 4:21 am
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Support team.

I have question related RESET_REQz/MCU_RESETz.

(1) I would like to know how to use RESET_REQz.

When this signal is asserted , does system go to WarmReset process ?

When this signal will not be used, I would like to know if this RESEST_REQz can be N/A (Open).

(2) I would like to know about MCU_RESETz.

I think that this signal will be asserted when MCU is reset. (Including POR and WarmReset).

If so, it can be used for controlling extrema module reset. Is my understanding correct ?

I would like to know if it needs to be connected with Pull up when it will not be used.

Best Regards

KORO

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AM3352: U-boot customization

August 15, 2019, 4:37 am
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Part Number: AM3352

#1. I would like to go through the uboot source code. where is the main function source file?

arch/arm/cpu/armv7/start.S

/*
* Setup vector:
* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
* Continue to use ROM code vector only in OMAP4 spl)
*/
#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
bic r0, #CR_V @ V = 0
mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register

/* Set vector address in CP15 VBAR register */
ldr r0, =_start
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
#endif

/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_cp15
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
bl cpu_init_crit
#endif
#endif

bl _main

 

#2. Is there a poring guide as that of old SDK in below page? or Will it be updated according to new version Processor SDK?

 

#3. How to boot custom board with the default uboot, which function which macro definition to modify?

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