Part Number: AM6546
Tool/software: TI C/C++ Compiler
I am running following program by following example given here https://gist.github.com/shirriff/2a7cf2f1adb37011da827f1c7f47b992
Interrupts are not getting cleared once set , in highlighted area below.
Anyone worked on this before can please guide here.
#define DELAY_NS 500 // Use 500000000 for 0.5 second delay
#define WRITE_PIN 15 /* P8_11, Ethernet output data, pr1_PRU0_pru_r30_15 */
// PRU ECAP control registers (i.e. PWM used as a timer)
#define ECAP 0x00030000 // ECAP0 offset, TRM 4.3.1.2
// Using APWM mode (TRM 15.3.2.1) to get timer (TRM 15.3.3.5.1)
#define ECAP_TSCTR ((volatile uint32_t *)(ECAP + 0x00)) // 32-bit counter register, TRM 15.3.4.1.1
#define ECAP_APRD ((volatile uint32_t *)(ECAP + 0x10)) // Period shadow, TRM 15.3.4.1.5, aka CAP3
#define ECAP_ECCTL2 ((volatile uint32_t *)(ECAP + 0x2a)) // Control 2, TRM 15.3.4.1.8
#define ECAP_ECEINT ((volatile uint16_t *)(ECAP + 0x2c)) // Enable interrupt, TRM 15.3.4.1.9
#define ECAP_INTFLG ((volatile uint16_t *)(ECAP + 0x2E)) // Enable interrupt, TRM 15.3.4.1.9
#define ECAP_ECCLR ((volatile uint16_t *)(ECAP + 0x30)) // Clear flags, TRM 15.3.4.1.11
// Forward definitions
void init_pwm();
void wait_for_pwm_timer();
void main(void)
{
uint32_t *pDdr = (uint32_t *) &CT_DDR;
// Globally enable host interrupts
CT_INTC.GLOBAL_ENABLE_HINT_REG = 0x1;
/* Clear any pending PRU-generated events */
__R31 = 0x00000000;
/* Start preparing message for host - make sure it's not 0xB */
pDdr[1] = 0x0001;
/* Enable Host interrupt 2 */
CT_INTC.HINT_ENABLE_SET_INDEX_REG |= HOST_NUM;
/* Map channel 2 to host 2 */
CT_INTC.HINT_MAP_REG0_bit.HINT_MAP_2 = HOST_NUM;
/* Map PRU0_ARM_INTERRUPT (event 19) to channel 2 */
CT_INTC.CH_MAP_REG4_bit.CH_MAP_19 = CHAN_NUM;
/* Ensure PRU0_ARM_INTERRUPT is cleared */
CT_INTC.STATUS_CLR_INDEX_REG = (PRU0_ARM_INTERRUPT - 16);
/* Enable PRU0_ARM_INTERRUPT */
CT_INTC.ENABLE_SET_INDEX_REG = (PRU0_ARM_INTERRUPT - 16);
/* Ensure CT_DDR (C31) is pointing to start of DDR memory (0x80000000) */
PRU0_CTRL.CTPPR1_bit.C31_BLK_POINTER = 0x0;
/* Write value of 0xB which Host will read after receiving the interrupt */
// = 0xB;
volatile int16_t y = 0;
int16_t x = 0;
uint16_t i = 0;
uint16_t P = 20;
uint16_t m = 514;
init_pwm();
while(i <= 1024 )
{
y = m - abs(m - 2*(i++ % m));
wait_for_pwm_timer();
}
/* Halt PRU core */
__halt();
}
// Initializes the PWM timer, used to control output transitions.
// Every DELAY_NS nanoseconds, interrupt 15 will fire
inline void init_pwm() {
// *PRU_INTC_GER = 1; // Enable global interrupts :already enabled
*ECAP_ECCLR = 0xff; // Clear interrupt flags
*ECAP_APRD = DELAY_NS / 5 - 1; // Set the period in cycles of 5 ns
*ECAP_ECCTL2 = (1<<9) /* APWM */ | (1<<4) /* counting */;
*ECAP_TSCTR = 0; // Clear counter
*ECAP_ECEINT = 0xC0; // Enable compare equal interrupt
*ECAP_ECCLR = 0xff; // Clear interrupt flags;inconsistent behavior
// Wait for the PWM timer to fire.
// see TRM 15.2.4.26
inline void wait_for_pwm_timer() {
// while (!(__R31 & (1 << 30))) {} // Wait for timer compare interrupt
<span style='background-color:#ffff00;'> while(!(*ECAP_INTFLG & 1)){};</span>
CT_INTC.STATUS_CLR_INDEX_REG = 15; // Clear interrupt
*ECAP_ECCLR = 0xff; // Clear interrupt flags
}
