Part Number: AM3352

Tool/software: TI C/C++ Compiler

Hi,

I am using 4.14 kernel for my AM3352 custom board with gpmc NOR flash as my boot device. But i am not able to enable my nor flash using compatible cfi-flash.

Same thing is working fine with 3.14 kernel. Issue seen with only 4.14 kernel. My MTD blocks are not enabled.

Please find below logs and device tree.

&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nor0_pin>;
gpmc,num-waitpins = <1>;
ranges = <0 0 0x08000000 0x04000000>; //0x08000000 is memory address and 64mb of NOR
#address-cells = <2>;
#size-cells = <1>;
nor@0,0 {
compatible = "cfi-flash";
linux,mtd-name = "winbond,xxxxxxxx";
reg = <0 0x00000000 0x04000000>;//64mb of flash
bank-width = <2>;//16-bit flash i.e width
#address-cells = <1>;
#size-cells = <1>;
use-advanced-sector-protection;

gpmc,mux-add-data = <2>;
gpmc,cs-on-ns = <5>;//20
gpmc,cs-rd-off-ns = <150>;
gpmc,cs-wr-off-ns = <150>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <10>;
gpmc,adv-wr-off-ns = <10>;
gpmc,oe-on-ns = <20>;
gpmc,oe-off-ns = <110>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <110>;
gpmc,rd-cycle-ns = <140>;
gpmc,wr-cycle-ns = <140>;
gpmc,access-ns = <120>;
gpmc,page-burst-access-ns = <30>;
gpmc,bus-turnaround-ns = <20>;
gpmc,cycle2cycle-delay-ns = <30>;
gpmc,wr-data-mux-bus-ns = <70>;
gpmc,wr-access-ns = <120>;

partition@0 {
label = "u-boot";

-------

logs:

[ 1.458116] pinctrl-single 44e10800.pinmux: pin PIN35 already requested by 4c
[ 1.469482] pinctrl-single 44e10800.pinmux: pin-35 (50000000.gpmc) status -22
[ 1.476977] pinctrl-single 44e10800.pinmux: could not request pin 35 (PIN35)e
[ 1.489745] omap-gpmc 50000000.gpmc: Error applying setting, reverse things k
[ 1.497528] omap-gpmc: probe of 50000000.gpmc failed with error -22 ------------------------------->this is the error for gpmc
[ 1.506147] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
[ 1.527153] rtc rtc1: invalid alarm value: 1970-5-25 25:84:0

Please help to solve this issue. Working fine with 3.14

Regards,

Subramanya

Part Number: AM3352

Part Number: TMS320C6678

Tool/software: Code Composer Studio

Hello,
I want to send and receive Direct I/O packets between DSP (C6678) and FPGA with 1.25, 2.5, 3.125, and 5 Gbps rates.

As a first step, I studied loopbackDioIsr example project of SRIO. But, there are several cases that need more to be clarified for me.

*******************************************************************************************************************************************

1- First question is about the following commands in the dioExampleTask function.

What is number 48 in these commands? Is it input event number 48 which is related to QM interrupt for queue 704 (in the following image)?

EventCombiner_dispatchPlug (48, (EventCombiner_FuncPtr)Srio_rxCompletionIsr, (UArg)hDrvManagedSrioDrv, TRUE);

EventCombiner_enableEvent(48);

*******************************************************************************************************************************************

2- In the previous commands in question 1, is the Srio_rxCompletionIsr function used for receiving NWRITE_R and NREAD requests?

Since the example NWRITE_R and NREAD requests are DIO operations, why the Srio_dioCompletionIsr function is not used?

*******************************************************************************************************************************************

3- Next question is about the following commands in the dioSocketsWithISR function.

As I studed, I think that Host Interrupts are CIC event outputs.

Is host interrupt 8 related to interrupt controller output 8 (CIC0_OUT8 or CIC1_OUT8) which is showned the following image?

/* The configuration is for CPINTC0. We map system interrupt 112 to Host Interrupt 8. */

CpIntc_mapSysIntToHostInt(0, CSL_CIC0_SRIO_INTDST0, 8);

/* Enable the Host Interrupt. */

CpIntc_enableHostInt(0, 8);

*******************************************************************************************************************************************

4- Next question is about the following commands in the myDioTxCompletionIsr function.

Why Srio_dioTxCompletionIsr is used in myDioTxCompletionIsr function?

static void myDioTxCompletionIsr ( UArg argument )
{
        /* Pass the control to the driver DIO Tx Completion ISR handler */
        Srio_dioTxCompletionIsr ((Srio_DrvHandle)argument, hSrioCSL);

        /* Wake up the pending task */
        srioLsuIsrServiced = 1;

        /* Debug: Increment the ISR count */
        srioDbgDioIsrCnt++;

        return;
}

*******************************************************************************************************************************************

5- Next question is about the following commands in the dioSocketsWithISR function.

Are these command used for checking the completion of the transmitting NWRITE_R and NREAD packets?

If yes, is the completion is considered after sending transmitting NWRITE_R and NREAD packets or is considered after receiving response packets related to NWRITE_R and NREAD packets?

/* Read the completion code filled by the ISR */
compCode = 0xFF;
if (Srio_getSockOpt(srioSocket[sockIdx], Srio_Opt_DIO_READ_SOCK_COMP_CODE, &compCode, sizeof(uint8_t)) < 0)
{
        System_printf ("Error: Unable to read the completion code in socket\n");
        return -1;
}

*******************************************************************************************************************************************

6- Since the example project tries to send NWRITE_R and NREAD requests and these requests needs response packets, where (which function) and when the response packet related to NWRITE_R and NREAD packets are generated in loopbackDioIsr example? 

Part Number: AM3352

Hi,

I would like to know, if we can call two separate functions for reboot and poweroff from a platform driver, like leds-gpio.c

Because, as far as I understand, reboot is triggering poweroff internally. Hence, I felt that there is no differentiation between reboot and poweroff at the platform driver level.

Is that true ?

Or can we differentiate between poweroff and reboot ?

Use case,

I would like to keep a GPIO as is (do not make it LOW explicitly), when reboot command is issued,

but, make it LOW when poweroff command is issued.

Part Number: AM5726

We are upgrading the SDK 05..03.0.00.7 on our customized board and facing issue of reboot command is not working if we can use the reboot -f  and it is working fine.

SDK : 05.03.00.07

[   39.883977] watchdog: watchdog0: watchdog did not stop!

[   39.895636] systemd-shutdow: 158 output lines suppressed due to ratelimiting
[   39.983483] systemd-shutdown[1]: Sending SIGTERM to remaining processes...
[   39.998960] systemd-journald[84]: Received SIGTERM from PID 1 (systemd-shutdow).
[   40.081458] systemd-shutdown[1]: Sending SIGKILL to remaining processes...
[   40.095874] systemd-shutdown[1]: Hardware watchdog 'OMAP Watchdog', version 0
[   40.105298] systemd-shutdown[1]: Unmounting file systems.
[   40.111149] systemd-shutdown[1]: Remounting '/' read-only with options 'data=ordered'.
[   40.155119] EXT4-fs (mmcblk0p2): re-mounted. Opts: data=ordered
[   40.172085] systemd-shutdown[1]: Remounting '/' read-only with options 'data=ordered'.
[   40.180330] EXT4-fs (mmcblk0p2): re-mounted. Opts: data=ordered
[   40.186389] systemd-shutdown[1]: All filesystems unmounted.
[   40.192092] systemd-shutdown[1]: Deactivating swaps.
[   40.197294] systemd-shutdown[1]: All swaps deactivated.
[   40.202798] systemd-shutdown[1]: Detaching loop devices.
<<<<<<<<<<<<<<<STUCK HERE >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

Part Number: TDA3MV

Dear Champs,

Is there any example or further details on DPC(Dead Pixel Correction) of TDA3 ISP?

Although my customer checked it on TRM, they could not understand how DPC registers(IPIPE_DPC_LUT_EN, IPIPE_DPC_LUT_SEL, IPIPE_DPC_LUT_ADR, IPIPE_DPC_LUT_SIZ) can be used exactly.

If there is any example or further details on these DPC registers, it would be helpful for my customer.

Thanks and Best Regards,

SI.

Part Number: OMAP-L138

Hi,

With reference to document  "Migrating a DSP/BIOS 5 Application to SYS/BIOS 6 (SPRAAS7G) "

In section 4.1 table 1 Module Mappings from DSP/BIOS 5 to SYS/BIOS 6

In the table headings, there are a columns name SYS/BIOS 6 Legacy Module and Recommended SYS/BIOS 6 Module

My questions :-

1) What are the difference between legacy and non legacy ?

2) Can both be used concurrently ? if yes how ? link in both library files ?

Thanks.

Part Number: TMS32TCI6614BSXCMS

The tci6614(TMS320TCI6614CCMSA) arm core sometimes can’t receive the ARP request and reply packet but can receive all the other packets at the same time.

We init the 3 port Ethernet switch in vlan aware mode. Set the switch port0 and switch port2 in vlan 1,the switch port0 and switch port1 in vlan 7. The switch port2 connect to FPGA, the switch port1 connect to a PHY to connect to PC for example. The tci6614 arm core sometimes can’t receive the ARP request and reply packet when running for a while maybe several days or 20 minutes. At this time, we get switch port0  statistics from the register 02090b34(TXGOODFRAMES) and 02090b38(TXBROADCASTFRAMES) and shows us that the 3 port Ethernet switch port0 can transmit the ARP request and reply packet to Packet Streaming Switch. But we can’t get any ARP request and reply packet in the interrupt handler(khwq_int_handler in the file keystone_hwqueue.c in the Linux kernel drivers/hwqueue directory). So we don’t know how the ARP request and reply packet dropped? Is it possible dropped in the PA module? How to debug to show it dropped in PA module? I try to configure to bypass the PA module, but failed. Can you tell us how to configure bypass the PA module? Or is there any other ways to know how the ARP packets dropped? 

PS:

1.      When the TCI6614 can receive ARP request and reply packet,we print out the packet information by calling the function netcp_dump_packet, and it shows us that the ARP request and reply packet has correct checksum, and there is no errors in the 3 port Ethernet switch statistics.

2.      When the TCI6614 arm core can’t receive ARP request and reply packet, we can see it can receive all the other packets from the switch port1 by calling the function netcp_dump_packet to show the packet information.

Part Number: PROCESSOR-SDK-DRA8X

Hi,

I get the following error message when I execute:

sudo ./oe-layertool-setup.sh -f configs/processor-sdk/processor-sdk-06.00.00.07-config.txt
[sudo] password for marcus:
/home/name/ti-processor-sdk-linux-automotive-j7-evm-06_00_00_00/yocto-build

cloning repo bitbake

Fetching origin
Switched to branch '1.40'
Your branch is up to date with 'origin/1.40'.
Already up to date.
Note: checking out '4ce92f43eeac6a4bfd06e8567fa6891614b5b3b0'.

You are in 'detached HEAD' state. You can look around, make experimental
changes and commit them, and you can discard any commits you make in this
state without impacting any branches by performing another checkout.

If you want to create a new branch to retain commits you create, you may
do so (now or later) by using -b with the checkout command again. Example:

  git checkout -b <new-branch-name>

HEAD is now at 4ce92f43 gitsm: Add need_update method to determine when we are going to a new SRCREV

cloning repo meta-processor-sdk

Fetching origin
Previous HEAD position was e5b633c packagegroups: opencl: extend tidl to dra7xx family
Switched to branch 'master'
Your branch is up to date with 'origin/master'.
Already up to date.
Note: checking out 'e5b633c0aa6d924ab6bea15906e3790c01c86633'.

You are in 'detached HEAD' state. You can look around, make experimental
changes and commit them, and you can discard any commits you make in this
state without impacting any branches by performing another checkout.

If you want to create a new branch to retain commits you create, you may
do so (now or later) by using -b with the checkout command again. Example:

  git checkout -b <new-branch-name>

HEAD is now at e5b633c packagegroups: opencl: extend tidl to dra7xx family

cloning repo meta-ros

Cloning into '/home/marcus/ti-processor-sdk-linux-automotive-j7-evm-06_00_00_00/yocto-build/sources/meta-ros'...
fatal: unable to access 'github.com/.../': gnutls_handshake() failed: An unexpected TLS packet was received.
ERROR: Could not clone repository at github.com/.../meta-ros.git
marcus@Latitude-E6530:~/ti-processor-sdk-linux-automotive-j7-evm-06_00_00_00/yocto-build$

Any idea what the root cause could be?

Many thanks and best regards

Marcus

Part Number: 66AK2G12

Hello.

I am trying to reduce boot up time.

Following is board configuration.

-. CPU : 66AK2G12, 1GHz
-. Boot mode : QSPI, 48MHz, single read.

Table 1 is the checked in my board.

Why does the phase 1) and 3) take so long time?

And is there any way to reduce the time?

Part Number: TDA2SX

Hi TI team.

My customer is developing ADAS using TDA2SX. 

During the EVM review, we found that the temperature increased a lot. Is there a guide document for temperature optimization?

Please check my request.

Thanks.

Part Number: AM3352

Hi,

We're in now in a process of bringing u board on AM3352 processor.
Of a 3 boards that can boot into U-Boot only one is able to boot kernel reliable - two others are stuck at "Starting kernel" and can start only once in a while.

To boot device into kernel, some U-Boom ddr-deffs were changed. We're using one bank M15T1G1664A (www.esmt.com.tw/.../M15T1G1664A(2C).pdf). Current DDR defs are:

/* Oya M15T1G1664A-DEB */
#define M15T1G1664A_IOCTRL_VALUE		0x3BD
#define M15T1G1664A_ZQ_CFG				0x50074BE4
#define M15T1G1664A_EMIF_SDCFG		(\
    (3 << 29) |  /* DDR3 memory  */\
    (0 << 27) | /*  */\
    (1 << 24) | /* RQZ/4 */\
    (1 << 23) | /* Differential DQS */\
    (1 << 21) | /* Dynamic ODT RZQ/4 */\
    (0 << 20) | /* Do not disable DDL */\
    (1 << 18) | /* Drive strength RZQ/7 */\
    (0 << 16) | /* CWL 5 */\
    (1 << 14) | /* 16 bit mode */\
    (4 << 10) | /* CAS 6 */\
    (4 << 7)  | /*  13 rows */\
    (3 << 4)  | /* 8 banks RAM */\
    (0 << 3)  | /*  */\
    (2 << 0)    /*  */\
    )

/* Core AC parameters */
#define M15T1G1664A_EMIF_READ_LATENCY	0x100007 /* CL6 + 1*/
#define M15T1G1664A_EMIF_TIM1			0x0888C39B
#define M15T1G1664A_EMIF_TIM2			0x28247FDA
#define M15T1G1664A_EMIF_TIM3			0x501F821F
#define M15T1G1664A_EMIF_SDREF			0x00000C30

#define M15T1G1664A_RATIO				0x80
#define M15T1G1664A_INVERT_CLKOUT		0x0
/* Calculated by software leveling */
#define M15T1G1664A_RD_DQS				0x45
#define M15T1G1664A_PHY_FIFO_WE			0x9A
#define M15T1G1664A_WR_DQS				0x66
#define M15T1G1664A_PHY_WR_DATA			0x90

 EMIF parameters was calculated by means of excel spreadsheets that can be found here.

As we didn't have JTAG to run Software leveling from CCS we've used one that can be found via this lin

IOCTRL_VALUE vas found by trial and error method.

With this parameters u-boot mtest runs without errors on all 3 boards. command we were using: mtest 0x80200000 0x87000000

Our boot configuration:

CONTROL: control_status = 0x00400324
  * SYSBOOT[15:14] = 01b (24 MHz)
  * SYSBOOT[11:10] = 00b No GPMC CS0 addr/data muxing
  * SYSBOOT[9] = 0 GPMC CS0 Ignore WAIT input
  * SYSBOOT[8] = 0 GPMC CS0 8-bit data bus
  * Device Type = General Purpose (GP)
  * SYSBOOT[7:6] = 00b MII (EMAC boot modes only)
  * SYSBOOT[5] = 1 CLKOUT1 enabled
  * Boot Sequence : UART0 -> XIP w/WAIT (MUX1) -> MMC0 -> NAND

We have no clues on why it can happen with identical hardware and software.
Maybe there is some parameters we're missing in our setup? Now we have JTAG so we can test something more if possible.

Part Number: AM5718

Tool/software: Code Composer Studio

Hii,

Can anybody help me finding the solutions for the below points ?

1. Where can I get the source code for flashWriter program ?

2. How can we change the default uart3 to uart1 to get the debug prints for RTOS QSPI/SD booting ?

3, Otherwise is there any way we can get the debug prints on the CCS console ?

Thanks and regards

Arpita Jena

Part Number: PROCESSOR-SDK-AM437X

Tool/software: Code Composer Studio

Hi,

I am looking for an example project using the UART with DMA support (on my AM437x EVM). I thus created the UART_BasicExample_dma_evmAM437x_armTestProject via the pdkProjectCreate.bat file and imported the project into a workspace. I then added a variable EDMA3LLD_BIOS6_INSTALLDIR to the directory C:\ti\edma3_lld_2_12_05_30D. (As the directory specified in the GNU linker which used this variable could not be found). To create the project I called:

- pdkProjectCreate.bat am437x evmAM437x little uart all arm

Now when building the example from CCS, I STILL receive warnings:

Please see the build log here in the following .txt file: (Please visit the site to view this file)

Why are these warnings present in an generated example project? Except for the PRCMModuleEnable function, I do not believe these are linking errors. So I do not understand how it can be that there are initializations from incompatible pointer types in example projects?

Could anyone please assist in getting these warnings fixed??

The following is true:

- CCS v9.1.0.00010

- pdk_am437x_1_0_14

- xdctools_3_55_02_22_core

- edma3_lld_2_12_05_30D

- compiler: GNU v7.2.1 (Linaro)

Regards,

Johnny

Part Number: TMDXIDK57X-LCD

Tool/software: TI C/C++ Compiler

Hi,

I'm trying to use imglib library to apply a simple 3x3 kernel (Gaussian filter) to an image, I use IMG_conv_3x3_i8_c8s, for that purpose, I have broken my input image into several iterations and each time I feed some rows of the image to IMG_conv_3x3_i8_c8s routine, I checked some first iterations and it is working correctly, but after some iterations, it starts to generate zeros, can anyone explain why that happens? how can I correct my code?

this is my input image known as cameraMan:

this is my output image with zeros for most parts:

this is my main.c:

/*
 *  ======== main.c ========
 */

#include <xdc/std.h>

#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <ti/imglib/imglib.h>
#include <ti/sysbios/BIOS.h>

#include <ti/sysbios/knl/Task.h>
#include "ImgCode.h"

#define imSize   256*256
#define Cols     256
#define Rows     256


const char myMask[] = {
                                     0, 1, 0,
                                     1,  2,  1,
                                     0,  1,  0
};



Void taskFxn(UArg a0, UArg a1)
{
    unsigned char  resultImage[(254)*(252)];
    int iter0=0,iter1=0;
     for(iter0=0,iter1=0; iter0<(256*256-3*256); iter0+=256,iter1+=252){
         IMG_conv_3x3_i8_c8s(&myImage[iter0], &resultImage[iter1], 252, 254, myMask, 3);
     }


}

/*
 *  ======== main ========
 */
Int main()
{ 
    Task_Handle task;
    Error_Block eb;

    System_printf("enter main()\n");

    Error_init(&eb);
    task = Task_create(taskFxn, NULL, &eb);
    if (task == NULL) {
        System_printf("Task_create() failed!\n");
        BIOS_exit(0);
    }

    BIOS_start();    /* does not return */
    return(0);
}

and this is my project folder:

(Please visit the site to view this file)

Im using sys/BIOS 6_75_02_00 , XDCtools 3_51_01_18, imglib_c66x_3_2_0_1 and CCS 9.1.0.

any help would be appreciated.

alex.

Part Number: PROCESSOR-SDK-OMAPL138

Tool/software: TI-RTOS

Hi,

I'm using the latest SDK (PDK 1_0_9).

My GPIO initialization function:

void Usm_board_initGPIO(void)
{

    GPIO_v0_HwAttrs gpio_cfg;
    /* Get the default init configurations */
    GPIO_socGetInitCfg(GPIO_PORT_NUM0, &gpio_cfg);
    /* Modify the default GPIO configurations if necessary and set*/
    GPIO_socSetInitCfg(GPIO_PORT_NUM0, &gpio_cfg);

    /* Set the bank interrupt */
    GPIO_socSetBankInt(GPIO_PORT_NUM0, GPIO_FPGA_GPIO0_2_PIN_NUM, NULL); //2U
    GPIO_socSetBankInt(GPIO_PORT_NUM0, GPIO_MMC_SDCD_PIN_NUM, NULL); //64U
    GPIO_socSetBankInt(GPIO_PORT_NUM0, GPIO_S4_SW5_PIN_NUM, NULL); //98U 

   //GPIO initialization
   GPIO_init(); 
}

I noticed problem with GPIO_init() function. This function set Hwi only for the first pin because inside function static void GPIO_setConfig_v0(uint32_t index, GPIO_PinConfig pinConfig)

set portHwiCreatedBitMask |= gpioPortIntBitMask, and Hwi for other is not made.

I made changes to the GPIO library but maybe there is another workaround?

Regards, Patryk

Part Number: TMS320C6678

Tool/software: Code Composer Studio

Hi,

In continue of my question  https://e2e.ti.com/support/processors/f/791/t/822540, I have another issue.

When the I configured the fpga bar size to 128MB, I can access only to the bar0 and I can not access to bar1.

And when I configured the fpga bar size to 1MB, I can access to the both bars.

Am I loss something?

Thanks,

Zvi

Part Number: AM3358

Hi,

I am trying to customize u-boot for show splash screen in my bbb (imgPinout):

CPU  : AM335X-GP rev 2.1
Model: TI AM335x BeagleBone Black

I followed this guide (downloaded Processor Linux SDK 03.02.00.05 and use u-boot version inside) and compile successfully but splashscreen not work despite there aren't any errors.

There are many steps that isn't clear, I hope someone can help me to fix the problem.

1)  am335x-fb use hdmi port for output data?

2)  I have edited:

#define GPIO_BACKLIGHT_EN       GPIO_TO_PIN(3, 17)

     with:

#define GPIO_BACKLIGHT_EN       GPIO_TO_PIN(2, 25)

     according with pinout (see imgPinout above) for enable backlight. It is correct?

3)  It seems like everything works but the display is off. Maybe Backlight is problem?

Post a little bit log when start:

U-Boot 2016.05-00305-g6b0168e2f8-dirty (Aug 13 2019 - 16:01:34 +0200)

CPU  : AM335X-GP rev 2.1
Model: TI AM335x BeagleBone Black
       Watchdog enabled
DRAM:  512 MiB
NAND:  0 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
reading uboot.env

** Unable to read "uboot.env" from mmc0:1 **
Using default environment

reading splash.bmp.gz
<ethaddr> not set. Validating first E-fuse MAC
Net:   eth0: ethernet@4a100000

Thank you in advance

Part Number: OMAP-L138

Hi,

I am looking for the qualification test report of the OMAPL138 SOC. The information I am looking is for the assurance that the EMAC/MDIO modules were verified/validated. 

Thanks

Part Number: TDA2SX

Hello, We are building an automotive based surveillance platform based on TDA2SX.

Can you share some details related to heat dissipation from the SoC ?

We are interested in understanding common heat sink designs used for processors.