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Compiler/AM3352: How to solve "cc1: error: unrecognized command line option ‘-std=gnu11" error?

August 6, 2019, 12:12 am
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Part Number: AM3352

Tool/software: TI C/C++ Compiler

Hi Team,

How to solve "cc1: error: unrecognized command line option ‘-std=gnu11"  error?


will@Workstation:~/ti-processor-sdk-linux-am335x-evm-06.00.00.07$ make u-boot
===================================
Building U-boot
===================================
make -j 8 -C /home/will/ti-processor-sdk-linux-am335x-evm-06.00.00.07/board-support/u-boot-* CROSS_COMPILE=/home/will/ti-processor-sdk-linux-am335x-evm-06.00.00.07/linux-devkit/sysroots/x86_64-arago-linux/usr/bin/arm-linux-gnueabihf- am335x_evm_config
make[1]: Entering directory `/home/will/ti-processor-sdk-linux-am335x-evm-06.00.00.07/board-support/u-boot-2019.01+gitAUTOINC+8b90adfb16-g8b90adfb16'
HOSTCC scripts/basic/fixdep
cc1: error: unrecognized command line option ‘-std=gnu11’
make[2]: *** [scripts/basic/fixdep] Error 1
make[1]: *** [scripts_basic] Error 2
make[1]: Leaving directory `/home/will/ti-processor-sdk-linux-am335x-evm-06.00.00.07/board-support/u-boot-2019.01+gitAUTOINC+8b90adfb16-g8b90adfb16'
make: *** [u-boot] Error 2

will@Workstation:~/ti-processor-sdk-linux-am335x-evm-06.00.00.07$ uname -a
Linux fone-HP-Z220-CMT-Workstation 3.5.0-23-generic #35~precise1-Ubuntu SMP Fri Jan 25 17:13:26 UTC 2013 x86_64 x86_64 x86_64 GNU/Linux

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Compiler/TDA2E: what is the maximum size of the dsp program stack could be set?

August 6, 2019, 12:12 am
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Part Number: TDA2E

Tool/software: TI C/C++ Compiler

Hi,

i tried to port some algorithm to dsp,

but when running a period of time,

the dsp looked like crash,

so i add the dsp program.stack in file "link_fw/src/rtos/bios_app_common/tda2ex/dsp1/Dsp1.cfg",

0x800 -> 0x4000,

at that time, it was considered feasible,

but when i have been testing for a long time recently,

it still have problems found on the systems,

so, i want to know what is the maximum size of dsp program.stack could be set?

my Development environment ,soc tda2eg, vision_sdk302, usecase tda2ex_exm_linux_all

SJay

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TMS320C6457: mcsdk_1_00_00_08 download link

August 6, 2019, 12:31 am
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AM5718: eMMC at 1.8V

August 6, 2019, 12:53 am
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Part Number: AM5718

I have attached a AM5718 eMMC chipset (IS21ES16G-JQLI)  to MMC2 of AM5718. 

Since the bank is configured for 1V8 voltage , IO voltage is selected as 1V8.

This different from the reference schematics of AM5718.

I would like to know whether the would be any issues with such a configuration. I will be porting Linux to this eMMC. 

Attached is the present schematics. I have used IDK as reference except for the voltage ranges.

(Please visit the site to view this file)

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TDA3XEVM: Nand gpmc driver supports 4bit BCH ECC algorithm

August 6, 2019, 1:02 am
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Part Number: TDA3XEVM

  1. In linux, it seems like gpmc driver supports  8bit and 16 bit BCH ECC algorithm, But our 8bit NAND hardware supports 4bit  ECC.  So our question, Is it possible to use 4bit ECC NAND with 8bit BCH algorithm? Or We need to write our own 4bit BCH ECC algorithm to support our 4bit ECC NAND hardware.
  2. In TI forums some of them answered, 4bit NAND ECC will work with 8Bit BCH algorithm. Please find the forum link below, https://e2e.ti.com/support/processors/f/791/t/612245 What is your opinion on this? Is this the right    way or bad way to do it.
  3. How to calculate our NAND timing parameters like (cstime, advtime..etc)? or Can we reuse the timing parameters from the device tree of gpmc? Our NAND size is 256MB with 8 bit bus width.
    https://elixir.bootlin.com/linux/latest/source/Documentation/devicetree/bindings/mtd/gpmc-nand.txt

Regards

Prakash 

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AM5716: Power supply capacitors

August 6, 2019, 1:17 am
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Part Number: AM5716

How many capacitors should I mount on the next terminal?
N16 VDDA_MPU_ABE
M14 VDDA_PER
R17 VDDA_DDR
R14 VDDA_GPU
P15 VDDA_PLL_SPARE
P14 VDDA_CORE_GMAC
P16 VDDA_VIDEO
N12 VDDA_DSP_IVA
N11 VDDA_DEBUG
AD16 VDDA_OSC_AD16
AE16 VDDA_OSC_AE16
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TDA3XEVM: Operating system in TDA3

August 6, 2019, 1:55 am
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Part Number: TDA3XEVM

Hi,

We have a TDA3x EV. I know it has TI - BIOS. We would like to grab the images using M4, run our own image processing based algorithm on the DSP's and get the results. We have binaries of our algorithm and it has ARM support. Our library is Linux and QNX based.

1. Can we have other OS on TDA3 M4's other TI - BIOS (Linux or µC/OS)?

2. If only TI - BIOS, can you please let me know how to use create a new use-case which uses our own algorithm header file and get the results? Can you point me to the similar use case example?

   

    Something like:

        capture (IPU1_0) -> Ourown_algorithm (DSP1) -> Display or Nullsrc

or     Nullsrc (IPU1_0) -> Ourown_algorithm (DSP1) -> Display

Please let me know

Thanking you

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66AK2G12: DDR3 Register Parameters sheet

August 6, 2019, 2:58 am
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Part Number: 66AK2G12

Dear All.

Now I am designing about the DDR3 timing by the document of K2 DDR3 Register Calc v1p60.
Please teach me about below questions of this document.

1.What mean is the comments 「not used」 on the PHY Registers sheet? Is this register no need to use forever?

2.What mean is the comments 「read-modify-write mask」 on the PHY Registers sheet?

I understand the read-modify-write. About mask, when write the register, is there need to mask some registers?

3.What mean is the comments 「Note: Used default values assuming Config Clock of 533MHz・・・・」 on the PHY Registers sheet?

We plan to use the clock of DDR3 is 400MHz.(Because our 66AK2G main clock is  600MHz.)So do we need to change the value 「Configration Clock Frequency(MHz) 533.33」「Configraiton Clock Period (ns) 1.88」?

4. Below is our parameters for DDR3. Please check and advise.We selected the DDR3 is MT41K256M16 125(1600) .

This items is from the document of K2 DDR3 Register Calc v1p60  on the Design Parameters sheet.

DDR3 Output Clock Frequency400.000
DeviceMT41K256M16 125 (1600)
DDR_TERMRZQ/4
DYN_ODTDisable ODT
SDRAM_DRIVERZQ/7
CAS_WRITE_LATENCYCWL = 6
Narrow Mode16-bit bus width
ECC ByteDisable
CAS_LATENCYCAS = 7
IBANK8 bank SDRAM

EBANKSingle Rank - only use CE0

PAGESIZE2048-word page - 11 column bits
ADDRESS_MIRRORINGAddress Mirroring Off
PHY Data ZORZQ/6 = 40 Ohms
PHY ACCC ZORZQ/7 = 34 Ohms
PHY ODTRZQ/4 = 60 Ohms
DDR3 or DDR3LDDR3L

Best Regards

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Compiler/TDA2E: after cold boot and run app.out, the system abnormal restart

August 6, 2019, 5:19 am
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Part Number: TDA2E

Tool/software: TI C/C++ Compiler

Hi,

Our own customized pcba version, some parts of the pcba have a cold boot restart phenomenon,


After doing a lot of tests,

I found that, as long as i don't execute the app.out,

there will be no system abnormal restart, which means that the system only runs to the kernel to complete.

However, if i execute app.out, it may have a restart after i see the system show something on screen,

and it's usually in the case of cold boot.


May I ask which part may be causing it, and which part can I trace and test it?

my Development environment ,soc tda2eg, vision_sdk302, usecase tda2ex_exm_linux_all

SJay

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AM5726: 4.14.79 kernel issue

August 6, 2019, 5:36 am
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Part Number: AM5726

Hello,

We were using 4.9.69 kernel.

We have set  reg->country_code = CTRY_UNITED_STATES; in "/drivers/net/wireless/ath/regd.c" and when board gets up we were able to see it in iw reg get command.

Same thing, we are doing in  4.14.79 kernel version but country_code is not getting set. Also as output of iw list there is "no IR" tag.

Frequencies:
* 5180 MHz [36] (30.0 dBm) (no IR)
* 5200 MHz [40] (30.0 dBm) (no IR)
* 5220 MHz [44] (30.0 dBm) (no IR)
* 5240 MHz [48] (30.0 dBm) (no IR)

Please help me to debug this issue.

Regards,

Prerak

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TMS320C6678: Safe power down sequencing

August 5, 2019, 2:14 pm
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Part Number: TMS320C6678

Complying with the SPRS691 C6678 DSP Core-Before-IO power sequencing requirements, we successfully boot and operate our C6678 DSP, but I have a question regarding power down.

In terms of equipment safety, I am curious if there is a recommended power down sequence in the case where a C6678 power rail falls outside of regulation limits.

 

Question 1:

In such a case I would think the power down sequence would be the exact reverse of the Core-Before-IO power up sequence described in SPRS691E, section 7.3.1.1.  Is this correct?

 

Question 2:

Secondly, in the event a C6678 power rail falls outside of regulation limits, should the resets (RESET_N, POR_N, RESETFULL_N) also be asserted in the reverse order of the Core-Before-IO power up sequence described in SPRS691E, section 7.3.1.1, or should they be asserted simultaneously?

 

I use an FPGA to control the power up / power down sequencing of the C6678 and want to make sure that my power down sequencing gives the DSP the best chance to survive such an event.

 

Thank you very much for your time,

Jim Sanchez

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TIDEP0084: Error in gateway demo

August 6, 2019, 6:33 am
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Part Number: TIDEP0084

I am trying to run the demo on rasberry pi with CoP application on CC1310 launchpad. I am getting the following error in IoT gateway application:

"Found Mac Co-Processor Version info is:
Transport: 3
Product: 1
Major: 2
Minor: 0
Maint: 1
----------------------------------------
Start the gateway application
Collector Running as Process id: 1303
Launching Node-JS gateway application in background

/home/pi/tidep0084/example/iot-gateway/node_modules/smartobject/node_modules/lwm2m-id/node_modules/enum/dist/enum.js:347
Enum.prototype[Symbol.iterator] = function () {
^
ReferenceError: Symbol is not defined
at /home/pi/tidep0084/example/iot-gateway/node_modules/smartobject/node_modules/lwm2m-id/node_modules/enum/dist/enum.js:347:18
at Object.<anonymous> (/home/pi/tidep0084/example/iot-gateway/node_modules/smartobject/node_modules/lwm2m-id/node_modules/enum/dist/enum.js:359:3)
at Module._compile (module.js:456:26)
at Object.Module._extensions..js (module.js:474:10)
at Module.load (module.js:356:32)
at Function.Module._load (module.js:312:12)
at Module.require (module.js:364:17)
at require (module.js:380:17)
at Object.<anonymous> (/home/pi/tidep0084/example/iot-gateway/node_modules/smartobject/node_modules/lwm2m-id/node_modules/enum/index.js:1:80)
at Module._compile (module.js:456:26)
Cannot start gateway application
Something seems wrong with the gateway app"

I tried deleting node-modules folder and re-running npm install, didn't help. Appreciate help on resolving error

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CCS/AM3358: How to handle dma for AM3358?

August 6, 2019, 6:39 am
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Part Number: AM3358

Tool/software: Code Composer Studio

I take over a repository for TMS320F2837x processor.  I need to modify it for AM3358. The repository use dma and mcbsp to make two systems to communicate. There is no mcbsp in AM3358. I plan to use mcasp instead. How to handle dma for AM3358? edma seem not to include AM3358. I will appreciate it If you can provide the example to use dma and mcasp for communicate. Thanks 

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AM3358: PRU ADC example questions

August 6, 2019, 6:43 am
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Part Number: AM3358

Hello,

I have modified TI's PRU_ADC_onChip example and PRU_edmaConfig example to work using a ping pong buffer configuration. I am using the AM3358 chip, the DMA and ADC configuration is being done on the PRU, and the FFT code has been written using FFTW.

Just to make sure my logic is correct, should I place the DMA/ADC configuration code in the /lib/firmware section and the FFT code will be placed in the userspace? Here is a reference to the TI examples I am talking about:

https://git.ti.com/pru-software-support-package/pru-software-support-package/trees/master/examples/am335x/PRU_ADC_onChip

https://git.ti.com/pru-software-support-package/pru-software-support-package/trees/master/examples/am335x/PRU_edmaConfig

Essentially, I am trying to create a ping pong buffer using the ADC and the data is being moved from the PRU memory to the linux host memory in the userspace using DMA, so the host can access the ADC data since the host can't directly access the PRU data memory. Overall, this is like the PRU_ADC_onChip example but instead of using RPMsg communication, I am using DMA. In short, the idea is that when the DMA moves a certain amount of ADC data to the linux host DDR memory, the host will perform an FFT on that data from an interrupt that fires once the DMA transfer is complete.

My last question is since the ADC/DMA configuration code is in the /lib/firmware, is the host able to know when the DMA transfer is complete by using something like a "while(waiting for DMA interrupt to trigger)"?

Thank you!

Best Regards,

Tyler

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AM5728: Reserving interrupt lines for RTOS jailhouse inmate

August 6, 2019, 7:02 am
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Part Number: AM5728

Hi there,

I'm working with Linux processor-sdk 05.02.00.10 and RTOS processor-sdk 4.03.00.05.
I successfully worked with jailhouse hypervisor on the AM5728 evaluation board.

Now I'm setting up a RTOS jailhouse inmate on a AM5728 based custom board and I'm trying to figure out which irq lines I need to reserve in the Linux kernel dts.

Going through

http://software-dl.ti.com/processor-sdk-linux/esd/docs/latest/linux/Foundational_Components_Virtualization.html

and analyzing ICSS_EMAC example, I see that additional irq's 44 127 129 136 137 are reserved in am572x-idk-jailhouse.dtsi.

I see the interruptNum arguments that are used when the  ICSS_EMAC RTOS inmate invokes HwiP_create() is invoked, but there's no connection between them and the numbers skipped in the dts.

Also, nodes in the dts that hold lines like

interrupts = <GIC_SPI xx IRQ_TYPE_LEVEL_HIGH>;

with matching numbers (44 127 129...) are not related to the ICSS_EMAC example.

How can I figure the irq numbers I need to skip for my RTOS app?

Thanks a lot,

Nir.

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TDA2P-ACD: DISPC Signal Mapping after DSS BT565 Workaround for TDA2x

August 6, 2019, 7:44 am
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Part Number: TDA2P-ACD

We want to connect TDA2P to a SDI serializer (GS1662) in our custom board. The SDI serializer is intended to work in CEA-861-D Standard Format 4 (1280x720p @59.94/60 Hz) and in 20-bit mode input. Hence beside CLK some syncs are needed (DE, HSYNC, VSYNC). Input Data to SDI serializer are expected: DIN[19:10] as Luma, and DIN[9:0] as Chroma. After discussing with our TI FAE, we should connect VOUT_D[19:0] from TDA2P to the SDI serializer and refer to 

www.ti.com/.../sprac23a.pdf

and

www.ti.com/.../sprac16a.pdf

Since the input to the DSS in YUV422 format, and DSS are configured to bypass all the processing blocks inside (DSS output in RGB16 data format) and send the bit exact output on the 16 bit output interface, the SDI serializer should get data from  VOUT_D[15:0] according to Table 13-117 DISPC LCD Data Output from TDA2P_Technical_Reference_Manual.

Can you be so kind to determine,
• where to find MSB and LSB of luma (y[7], y[0]) and
• where to find MSB and LSB of chroma (uv[7], uv[0]) at TDA2P VOUT_D[15:0] ?

Thanks and Regards,

Andi

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PROCESSOR-SDK-TDAX: McSPI2 fails on reset on custom TDA2Px board

August 6, 2019, 8:07 am
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Part Number: PROCESSOR-SDK-TDAX

Hello,

when intializing McSPI2 as master in interrupt mode the device will fail with an error after the accessing the SOFTRESET bit in MCSPI_HL_SYSCONFIG (GIO_create -> mcspiMdCreateChan -> McSPIReset). The baseadress argument to the function McSPIReset is correct as far as I can tell. All instance and channel handles have been setup correctly. I'm using VisionSDK 3.3.0.0 with PDK 1.9.0.17.

The same code works for initializing McSPI1 as slave (also in interrupt mode). To make sure initializing McSPI1 does not influence the other instance I tried to exclude McSPI1 but nothing changed.

When running the code on different custom TDA3x board the initialization works as expected.

Do you know what might cause this error at this specific location? What else could I check?

Thanks for the help.

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TMS320DM8168: RTC only mode

August 6, 2019, 8:29 am
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Part Number: TMS320DM8168

Dear Sir,
              Will TMS320DM8168 processor support RTC only mode when power goes down. If yes, could you please suggest us, which are all power supply pins needs to be considered for running RTC only mode in Da Vinci processor(TMS320DM8168CCYGA2), please share us if any reference circuit for the same.
 
Thanks & Regards
Soundath G V
 
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Linux: VisionSDK settings for 800x600 and 1024x768 display resolution

August 6, 2019, 8:58 am
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Tool/software: Linux

We have designed a custom board, that is interfaced to a display with resolution.

We have modified the dts file and settings in chains file to set the resolution to 800x600. However, need help in setting other parameters as front porch & back porch to correct the display.

The image appears to be shifted on left and also weston screen gets cropped.

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CCS/AM3358: what is the difference between I2C and PRUSS-I2C f/w?

August 6, 2019, 9:16 am
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Part Number: AM3358

Tool/software: Code Composer Studio

I see two driver I2C and PRUSS-I2C f/w for AM3358.

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