Part Number: PROCESSOR-SDK-AM65X

error:

ERROR: nativesdk-ti-llvm3.6-3.6-r7 do_fetch: Fetcher failure: Fetch command export PSEUDO_DISABLED=1; export DBUS_SESSION_BUS_ADDRESS="unix:path=/run/user/1000/bus"; export SSH_AGENT_PID="2034"; export SSH_AUTH_SOCK="/run/user/1000/keyring/ssh"; export PATH="/home/adas/tisdk/build/arago-tmp-external-arm-toolchain/work/x86_64-nativesdk-arago-linux/nativesdk-ti-llvm3.6/3.6-r7/recipe-sysroot-native/usr/bin/perl-native:/home/adas/tisdk/build/arago-tmp-external-arm-toolchain/work/x86_64-nativesdk-arago-linux/nativesdk-ti-llvm3.6/3.6-r7/recipe-sysroot-native/usr/bin/python-native:/home/adas/tisdk/build/arago-tmp-external-arm-toolchain/work/x86_64-nativesdk-arago-linux/nativesdk-ti-llvm3.6/3.6-r7/recipe-sysroot-native/usr/bin/chrpath-native:/home/adas/tisdk/sources/oe-core/scripts:/home/adas/tisdk/build/arago-tmp-external-arm-toolchain/work/x86_64-nativesdk-arago-linux/nativesdk-ti-llvm3.6/3.6-r7/recipe-sysroot-native/usr/bin/x86_64-arago-linux:/home/adas/tisdk/build/arago-tmp-external-arm-toolchain/work/x86_64-nativesdk-arago-linux/nativesdk-ti-llvm3.6/3.6-r7/recipe-sysroot/tmp/xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx/yyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyy/sysroots/x86_64-arago-linux/usr/bin/crossscripts:/home/adas/tisdk/build/arago-tmp-external-arm-toolchain/work/x86_64-nativesdk-arago-linux/nativesdk-ti-llvm3.6/3.6-r7/recipe-sysroot-native/usr/sbin:/home/adas/tisdk/build/arago-tmp-external-arm-toolchain/work/x86_64-nativesdk-arago-linux/nativesdk-ti-llvm3.6/3.6-r7/recipe-sysroot-native/usr/bin:/home/adas/tisdk/build/arago-tmp-external-arm-toolchain/work/x86_64-nativesdk-arago-linux/nativesdk-ti-llvm3.6/3.6-r7/recipe-sysroot-native/sbin:/home/adas/tisdk/build/arago-tmp-external-arm-toolchain/work/x86_64-nativesdk-arago-linux/nativesdk-ti-llvm3.6/3.6-r7/recipe-sysroot-native/bin:${DEF_TOOLCHAIN_PATH}/bin:/home/adas/tisdk/sources/bitbake/bin:/home/adas/tisdk/build/arago-tmp-external-arm-toolchain/hosttools"; export HOME="/home/adas"; tar -xzf /home/adas/tisdk/downloads/git2_git.ti.com.opencl.clang.git.tar.gz failed with exit code 2, output:

gzip: stdin: unexpected end of file
tar: Unexpected EOF in archive
tar: Unexpected EOF in archive
tar: Error is not recoverable: exiting now

ERROR: nativesdk-ti-llvm3.6-3.6-r7 do_fetch: Fetcher failure for URL: 'git://git.ti.com/opencl/clang.git;protocol=git;branch=release_36_ti;destsuffix=git/tools/clang;name=clang'. Unable to fetch URL from any source.
ERROR: nativesdk-ti-llvm3.6-3.6-r7 do_fetch: Function failed: base_do_fetch
ERROR: Logfile of failure stored in: /home/adas/tisdk/build/arago-tmp-external-arm-toolchain/work/x86_64-nativesdk-arago-linux/nativesdk-ti-llvm3.6/3.6-r7/temp/log.do_fetch.18813
ERROR: Task (virtual:nativesdk:/home/adas/tisdk/sources/meta-arago/meta-arago-extras/recipes-core/llvm/ti-llvm3.6_3.6.bb:do_fetch) failed with exit code '1'

Part Number: AM5728

Hi,

Processor: AM5728

PDK: 

I'm wroking on RTOS project. I need to use UART3, 4, 5 ,6 ,7 ,8 ,9 and 10 in my project. Bu i have some issues with some uarts. My clock and pinmux configuration show below:

CLOCK CONFIGURATION:

// UART3
CSL_FINST(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_MODULEMODE, ENABLE);

while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST_FUNC !=
CSL_FEXT(l4PerCmReg->CM_L4PER_UART3_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER_UART3_CLKCTRL_REG_IDLEST));

// UART4
CSL_FINST(l4PerCmReg->CM_L4PER_UART4_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER_UART4_CLKCTRL_REG_MODULEMODE, ENABLE);

while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART4_CLKCTRL_REG_IDLEST_FUNC !=
CSL_FEXT(l4PerCmReg->CM_L4PER_UART4_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER_UART4_CLKCTRL_REG_IDLEST));

// UART5
CSL_FINST(l4PerCmReg->CM_L4PER_UART5_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER_UART5_CLKCTRL_REG_MODULEMODE, ENABLE);

while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_UART5_CLKCTRL_REG_IDLEST_FUNC !=
CSL_FEXT(l4PerCmReg->CM_L4PER_UART5_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER_UART5_CLKCTRL_REG_IDLEST));

// UART6
CSL_FINST(ipuCmReg->CM_IPU_UART6_CLKCTRL_REG,
IPU_CM_CORE_AON_CM_IPU_UART6_CLKCTRL_REG_MODULEMODE, ENABLE);

while(CSL_IPU_CM_CORE_AON_CM_IPU_UART6_CLKCTRL_REG_IDLEST_FUNC !=
CSL_FEXT(ipuCmReg->CM_IPU_UART6_CLKCTRL_REG,
IPU_CM_CORE_AON_CM_IPU_UART6_CLKCTRL_REG_IDLEST));

// UART7
CSL_FINST(l4PerCmReg->CM_L4PER2_UART7_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART7_CLKCTRL_REG_MODULEMODE, ENABLE);

while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART7_CLKCTRL_REG_IDLEST_FUNC !=
CSL_FEXT(l4PerCmReg->CM_L4PER2_UART7_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART7_CLKCTRL_REG_IDLEST));

// UART8

CSL_FINST(l4PerCmReg->CM_L4PER2_UART8_CLKCTRL_REG,

L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART8_CLKCTRL_REG_MODULEMODE, ENABLE);

while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART8_CLKCTRL_REG_IDLEST_FUNC !=
CSL_FEXT(l4PerCmReg->CM_L4PER2_UART8_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART8_CLKCTRL_REG_IDLEST));

// UART9
CSL_FINST(l4PerCmReg->CM_L4PER2_UART9_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_MODULEMODE, ENABLE);

while(CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_IDLEST_FUNC !=
CSL_FEXT(l4PerCmReg->CM_L4PER2_UART9_CLKCTRL_REG,
L4PER_CM_CORE_COMPONENT_CM_L4PER2_UART9_CLKCTRL_REG_IDLEST));

// UART10
CSL_FINST(wkupAonCmReg->CM_WKUPAON_UART10_CLKCTRL_REG,
WKUPAON_CM_CM_WKUPAON_UART10_CLKCTRL_REG_MODULEMODE, ENABLE);

while(CSL_WKUPAON_CM_CM_WKUPAON_UART10_CLKCTRL_REG_IDLEST_FUNC !=
CSL_FEXT(wkupAonCmReg->CM_WKUPAON_UART10_CLKCTRL_REG,
WKUPAON_CM_CM_WKUPAON_UART10_CLKCTRL_REG_IDLEST));

PINMUX CONFIGURATION:

/* UART3 - uart3_rxd on V2 - X_UART3 */
{0x1648, 0xE0000, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART3 - uart3_txd on Y1 - X_UART3 */
{0x164C, 0x90000, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART3 - uart3_ctsn on G17 - X_UART3 */
{0x17C8, 0xE0001, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART3 - uart3_rtsn on B24 - X_UART3 */
{0x17CC, 0x90001, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART5 - uart5_rxd on F11 - X_UART5 */
{0x15DC, 0x60002, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART5 - uart5_txd on G10 - X_UART5 */
{0x15E0, 0x10002, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART4 - uart4_rxd on G16 - Y_UART4 */
{0x173C, 0x50004, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART4 - uart4_txd on D17 - Y_UART4 */
{0x1740, 0x10004, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART6 - uart6_rxd on E8 - Y_UART6 */
{0x15FC, 0x60002, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART6 - uart6_txd on D9 - Y_UART6 */
{0x1600, 0x10002, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART7 - uart7_rxd on B7 - Y_UART7 */
{0x161C, 0x50002, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART7 - uart7_txd on B8 - Y_UART7 */
{0x1620, 0x10002, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART8 - uart8_rxd on C18 - Y_UART8 */
{0x1734, 0x50003, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART8 - uart8_txd on A21 - Y_UART8 */
{0x1738, 0x10003, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART9 - uart9_rxd on AA3 - Y_UART9 */
{0x1744, 0x50003, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART9 - uart9_txd on AB9 - Y_UART9 */
{0x1748, 0x10003, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART10 - uart10_rxd on D1 - Y_UART10 */
{0x1570, 0x60008, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

/* UART10 - uart10_txd on E2 - Y_UART10 */
{0x1574, 0x10008, {0x0, 0, 0}, {0x0, 0, 0}, {0x0, 0, 0}},

UART5, UART6, UART3 and UART10 working properly but UART4, UART9, UART7 and UART8 not working. 

UART_Open, command return ok but UART_write do noting.

Can you check my configuration settings. Where was my mistakes??

Thanks.

Metin Sunan

Part Number: AM6548

Hi

i just tired to run the create-sdcard.sh in the SDK6.0.0.7 and it seems it can't find the sdk directory with the prebuild images. So i did a diff between the sdk 5.03x and sdk 6.0.0.7  and t seems that the name for the root SDK in the create-sdcard.sh is different than the one we used to have. But the installation directory for sdk 6.0.0.7 is still very similar to the sdk 5.3.0.0? I like to understand why this was done if that is the case then we need to either change the installation directory or the script. Below is the diff and you can see that 

diff ./bin/create-sdcard.sh ~/ti-processor-sdk-linux-am65xx-evm-05.03.00.07/bin/create-sdcard.sh
77c77
< PARSEPATH=`echo $THEPWD | grep -o '.*ti-sdk.*.[0-9]/'`
---
> PARSEPATH=`echo $THEPWD | grep -o '.*ti-processor-sdk-linux-am65xx-evm-05.03.00.07/'`
691c691
< THEEVMSDK=`echo $PARSEPATH | grep -o 'ti-sdk-.*[0-9]'`
---
> THEEVMSDK=`echo $PARSEPATH | grep -o 'ti-processor-sdk-linux-am65xx-evm-05.03.00.07'`
708c708
< PARSEPATH=`echo $SDKFILEPATH | grep -o '.*ti-sdk.*.[0-9]/'`
---
> PARSEPATH=`echo $SDKFILEPATH | grep -o '.*ti-processor-sdk-linux-am65xx-evm-05.03.00.07/'`
719c719
< THEEVMSDK=`echo $SDKFILEPATH | grep -o 'ti-sdk-.*[0-9]'`
---
> THEEVMSDK=`echo $SDKFILEPATH | grep -o 'ti-processor-sdk-linux-am65xx-evm-05.03.00.07'`
770c770
< ls --sort=size $ROOTFILEPARTH | grep "tisdk.*rootfs" | grep 'tar.xz' | grep -n '' | awk {'print " " , $1'}
---
> ls $ROOTFILEPARTH | grep "tisdk.*rootfs" | grep 'tar.xz' | grep -n '' | awk {'print " " , $1'}
774c774
< FOUNDTARFILENAME=`ls --sort=size $ROOTFILEPARTH | grep "rootfs" | grep 'tar.xz' | grep -n '' | grep "${TARNUMBER}:" | cut -c3- | awk {'print$1'}`
---
> FOUNDTARFILENAME=`ls $ROOTFILEPARTH | grep "rootfs" | grep 'tar.xz' | grep -n '' | grep "${TARNUMBER}:" | cut -c3- | awk {'print$1'}`

Part Number: TMS320C6678

I've got Clock_doTIck configured to run every 20 us. It typically runs quite fast (<1us). But sometimes it runs very long (>15us).

Is there something I can do to reduce this? I need to run a HWI / SWI pair at 100 kHz on this core, and these long-running HWI Clock ticks are killing me!

I've attach my Execution Graph, along with my config and makefile (zipped).(Please visit the site to view this file)

Part Number: TMS320C6678

Complying with the SPRS691 C6678 DSP Core-Before-IO power sequencing requirements, we successfully boot and operate our C6678 DSP, but I have a question regarding power down.

In terms of equipment safety, I am curious if there is a recommended power down sequence in the case where a C6678 power rail falls outside of regulation limits.

Question 1:

In such a case I would think the power down sequence would be the exact reverse of the Core-Before-IO power up sequence described in SPRS691E, section 7.3.1.1.  Is this correct?

Question 2:

Secondly, in the event a C6678 power rail falls outside of regulation limits, should the resets (RESET_N, POR_N, RESETFULL_N) also be asserted in the reverse order of the Core-Before-IO power up sequence described in SPRS691E, section 7.3.1.1, or should they be asserted simultaneously?

I use an FPGA to control the power up / power down sequencing of the C6678 and want to make sure that my power down sequencing gives the DSP the best chance to survive such an event.

Thank you very much for your time,

Jim Sanchez

Part Number: AM3359

I have a custom board design based on the AM3359 that I'm having difficulty bringing up.  To simplify bringing up uboot & the kernel, much of the design is based on the Beaglebone Black schematic (same connections to SD card, same DDR3 memory part number connected in same manner).  I'm using CCS 9.1 and a Spectrum Digital XDS200 for troubleshooting.

I've been following the advice from http://processors.wiki.ti.com/index.php/AM335x_board_bringup_tips#DDR_configuration and could use some help on what to try next.

From CCS, if I open a memory browser window and try to access the memory at 0x0800 0000, I don't get anything. The MMU is off.

I've run the am335x-boot.dss boot analysis script and verified that the boot order is MMC1->MMC0->UART0->USB0.  I've brought the clock out (sysboot[5] = 1) and verified that it's 24MHz as expected.

I have an SD card that successfully boots the Beaglebone Black that I'm trying to use on the custom board.  If I power the board without the SD card, I get the stream of Cs on UART0 that are expected.

If I try to power the board with the SD card in the SD card slot (attached to MMC0), I don't get any console output on UART0 – was hoping to make it at least to uboot. The program counter is in the dead loop at 0x0002 0088 corresponding to a pre-fetch abort exception.

If I were having an issue with power sequencing, I don’t believe I would have made it as far as executing ROM code – is this correct?  Should I be able to read/write from the DDR3 from the memory browser prior to coding any board-specific DDR3 timing?  Could I please get some help as to what to try next?

Thanks!

Part Number: TMS320C6678

Hello, was wondering if anyone heard when or if there will be some enhancements to the TMS320C6678 DSP processors? For example, more memory, more ethernet ports, etc.

I know that I could try the 66AKHx line of processors but I don't want to mess with an ARM processor(s), too complex for my needs.

Thank you,

Joe

Part Number: AM3358

Tool/software: Code Composer Studio

Where are various EALLOW protected registers defined? What should I do to let my app can recognize keyword EALLOW and EDIS? Right now my app can't recognize keyword EALLOW and EDIS and compile failed.

Part Number: AM3358

Tool/software: Code Composer Studio

CCSv8 can't recognize MCSPI_Loopback_evmAM335x_armExampleProject, not ccs project file. So I can't import this project.

Part Number: PROCESSOR-SDK-AM335X

Hello -

I am trying to connect to a beagle bone black that has been extended and because of that it has no sd card.  trying to connect via uart ideally to download the bootloader and ultimately the linux kernel . ethernet or usb would be fine as well.  even jtag..  I am assuming I should be able to download what ever is current on a freshly installed ubuntu version with the current linux-processor-sdk and be able to build uboot and get the system loaded onto a beaglebone black.  Apparently not.  I have googled and downloaded and built and have had blockages in every part.  I think the problem is that I cannot seem to find a current set of versions that work together to do this job.  I wonder if there is a CURRENT description of exactly what tools to use and where to find them to do this pretty fundamental thing. I have beaglebone black and the basic evm .  I have the latest ccs version (9.x.x).  It is not clear which linaro version to use for compiling any of it.  Is there a clear path that most people use?  Uniflash looks pretty good but I cant even find the processor in the list.  Is is a mistake to think the sitara am335x has support ?  Can someone please point me in the right direction?  Any advice on the easiest and quickest approach would be valuable as well.

Thanks

Mark

Part Number: TDA3XEVM

Hi,

The FFT plugin has the following code logic where it's checking the FFT mode (Horizontal, Vertical or Both) on a per frame basis. If I added a control function to change this mode on the fly, would the plugin be able to output 1st FFT (Range FFT) if that mode was requested?

Int32 AlgorithmFxn_RadarFftProcess(void *alg_handle,
System_Buffer *in_buf,
System_Buffer *out_buf)
{
Int32 status = SYSTEM_LINK_STATUS_SOK;
AlgorithmFxn_RadarFftObj *pObj;
System_VideoFrameBuffer *pInputVideoBuffer;
System_VideoFrameBuffer *pOutputVideoBuffer;
UInt8 *inBufAddr, *outBufAddr, *metaDataBuffAddr, *coeffAddr;
AlgorithmFxn_RadarFftCreateParams *algLinkParams;
UInt32 currProfile = 0U;
UInt16 nextPowerOf2;
UInt32 chId;

//Vps_printf("AlgorithmFxn_RadarFftProcess: Start of Range/Doppler FFTs");

pObj = (AlgorithmFxn_RadarFftObj *)alg_handle;

pInputVideoBuffer = (System_VideoFrameBuffer *)in_buf->payload;
pOutputVideoBuffer = (System_VideoFrameBuffer *)out_buf->payload;

inBufAddr = (UInt8 *)pInputVideoBuffer->bufAddr[0];
outBufAddr = (UInt8 *)pOutputVideoBuffer->bufAddr[0];
metaDataBuffAddr = (UInt8 *)pOutputVideoBuffer->metaBufAddr;

chId = in_buf->chNum;
algLinkParams = &pObj->algLinkCreateParams;

if (( algLinkParams->algFFTMode == RADAR_FFT_MODE_HORIZONTAL ) ||
( algLinkParams->algFFTMode == RADAR_FFT_MODE_VERTICAL ))
{
pObj->pProcessInArgs->inAlgArgs[0].inBufs.bufDesc[FFT_TI_BUFDESC_IN_LISTBUFFER]->bufPlanes[0].buf =
inBufAddr + pObj->inBufAddrOffset[chId];
pObj->pProcessInArgs->inAlgArgs[0].outBufs.bufDesc[FFT_TI_BUFDESC_OUT_BUFFER]->bufPlanes[0].buf = outBufAddr;
pObj->pProcessInArgs->inAlgArgs[0].outBufs.bufDesc[FFT_TI_BUFDESC_OUT_BUFFER]->bufPlanes[0].width = 0;
}
else if(algLinkParams->algFFTMode == RADAR_FFT_MODE_HORZ_AND_VERT)
{
// Khai: This is the 1st FFT input and output buffers
// - input: inBufAddr + pObj->inBufAddrOffset[chId]
// - output: pObj->intermediateBuf -----------------> This is the 1st FFT output buffer
pObj->pProcessInArgs->inAlgArgs[0].inBufs.bufDesc[FFT_TI_BUFDESC_IN_LISTBUFFER]->bufPlanes[0].buf =
inBufAddr + pObj->inBufAddrOffset[chId];
pObj->pProcessInArgs->inAlgArgs[0].outBufs.bufDesc[FFT_TI_BUFDESC_OUT_BUFFER]->bufPlanes[0].buf = pObj->intermediateBuf;
pObj->pProcessInArgs->inAlgArgs[0].outBufs.bufDesc[FFT_TI_BUFDESC_OUT_BUFFER]->bufPlanes[0].width = 0;

// Khai: This is the 2nd FFT input and output buffers
// - input: pObj->intermediateBuf -----------------> Input to 2nd FFT processing is the 1st FFT intermediateBuf
// - output: outBufAddr
pObj->pProcessInArgs->inAlgArgs[1].inBufs.bufDesc[FFT_TI_BUFDESC_IN_LISTBUFFER]->bufPlanes[0].buf = pObj->intermediateBuf;
pObj->pProcessInArgs->inAlgArgs[1].outBufs.bufDesc[FFT_TI_BUFDESC_OUT_BUFFER]->bufPlanes[0].buf = outBufAddr;
pObj->pProcessInArgs->inAlgArgs[1].outBufs.bufDesc[FFT_TI_BUFDESC_OUT_BUFFER]->bufPlanes[0].width = 0;
}

Thanks,

--Khai

Part Number: TDA2SX

Dear Champs,

My customer would like to confirm the max muxed channels that VIP (Video Input Port) can support for 720p embeded sync input.

Per the spec, VIP can support up to 165Mhz pixel clock. My estimation is as follows. Could you help check if my estimation is correct?

BT.1120 (16bit)

For 720p60, the required pixel clock is 74.25MHz. VIP can support up to 2 ch muxed.

For 720p30, the required pixel clock is 37.125. VIP can support up to 4 ch muxed.

BT.656 (8.bit)

 For 720p30, the required pixel clock is 74.25MHz. VIP can support up to 2 ch muxed.

For 720p60, the required pixel clock is 148.5MHz. VIP can support up to 1 ch muxed.

Hi 

   We changed QSPI to from 48MHz to 76.8MHz, also have checked code in [SBLUtilsScaleIODelay]

   We find [gPadDelayConfigCommon_1_0], [gPadDelayConfigGpmcPadOther_1_0], the list seems too many IO pins for us, and some pins in the list drive off some modules such as I2C,

   So we remove the list [gPadDelayConfigCommon_1_0], [gPadDelayConfigGpmcPadOther_1_0] and only do IO ReCalibration for QSPI as below [gPadDelayConfigGpmcPadQSPI],

   Then we want to know if it is possible for us only do the IO ReCalibration with [gPadDelayConfigGpmcPadQSPI]?

static sblutilsPadDelayConfig_t gPadDelayConfigGpmcPadQSPI[] = {
/* CTRL_CORE_PAD_GPMC_A3 -> QSPI1_CS2 (PIN_INPUT) MANUAL delaymode */
{ 0x04C, 0x00070101, { 0x0000, 0, 0 }, { 0x0000, 0, 0 }, { 0x0218, 0, 0 } },
/* CTRL_CORE_PAD_GPMC_A4 -> QSPI1_CS3 (PIN_INPUT) MANUAL delaymode */
{ 0x050, 0x00070101, { 0x0000, 0, 0 }, { 0x0000, 0, 0 }, { 0x0224, 0, 0 } },
/* CTRL_CORE_PAD_GPMC_A13 -> QSPI1_RTCLK (PIN_INPUT) MANUAL delaymode */
{ 0x074, 0x00070101, { 0x0144, 0, 0 }, { 0x0000, 0, 0 }, { 0x0000, 0, 0 } },
/* CTRL_CORE_PAD_GPMC_A14 -> QSPI1_D3 (PIN_INPUT) MANUAL delaymode */
{ 0x078, 0x00070101, { 0x0150, 0, 0 }, { 0x0000, 0, 0 }, { 0x0000, 0, 0 } },
/* CTRL_CORE_PAD_GPMC_A15 -> QSPI1_D2 (PIN_INPUT) MANUAL delaymode */
{ 0x07C, 0x00070101, { 0x015C, 0, 0 }, { 0x0000, 0, 0 }, { 0x0000, 0, 0 } },
/* CTRL_CORE_PAD_GPMC_A16 -> QSPI1_D0 (PIN_INPUT) MANUAL delaymode */
{ 0x080, 0x00070101, { 0x0168, 0, 0 }, { 0x0000, 0, 0 }, { 0x0170, 0, 0 } },
/* CTRL_CORE_PAD_GPMC_A17 -> QSPI1_D1 (PIN_INPUT) MANUAL delaymode */
{ 0x084, 0x00070101, { 0x0174, 0, 0 }, { 0x0000, 0, 0 }, { 0x0000, 0, 0 } },
/* CTRL_CORE_PAD_GPMC_A18 -> QSPI1_SCLK (PIN_INPUT) MANUAL delaymode */
{ 0x088, 0x00070101, { 0x0000, 0, 0 }, { 0x0000, 0, 0 }, { 0x0188, 151, 0 } },
/* CTRL_CORE_PAD_GPMC_CS2 -> QSPI1_CS0 (PIN_INPUT) MANUAL delaymode */
{ 0x0B8, 0x00070101, { 0x0000, 0, 0 }, { 0x0000, 0, 0 }, { 0x0374, 0, 0 } },
/* CTRL_CORE_PAD_GPMC_CS3 -> QSPI1_CS1 (PIN_INPUT) MANUAL delaymode */
{ 0x0BC, 0x00070101, { 0x0000, 0, 0 }, { 0x0000, 0, 0 }, { 0x0380, 22, 0 } },
};

Part Number: PROCESSOR-SDK-TDAX

Hi,

In TDA4, there are many cores.

Where can I find the Max. Hz each core(A72, C66, C71, DNN IP and so on)?

Could you let me know about this?

BR,

Heechang

Part Number: AM3352

Hi,

My customer is using AM3352.

From datasheet revision K, Input rise time/fall time requirements are added.
The maximum is 10nsec.

In customer’s system, an external device with open-drain signal is connected to UART inputs.
And internal pulls are used to drive the signals to high.
As internal pulls are weak, it is not possible to drive the signal to high in 10nsec.
Does this cause any issues in real life?
Why the maximum rise time is added now?

Thanks and regards,
Koichiro Tashiro

Part Number: AM4378

Hello,

I designed a board broadly based on AM437x-gp-evm. We use SDK 4.02. We develop QT application using sitara cross compiler.

How can i add  library for "sound" in QT in AM4378 SDK.

Regards,

Winiston.P

Part Number: AM5718

Hi,

I am using AM5718 IDK EVM and ti-processor-sdk-linux-am57xx-evm-05.03.00.07.

I am carrying out the activity of booting EVM with minimum peripherals (UART3, eth0,I2c, QSPI1, MMC1.).My aim is to make sure that our custom board will boot with the given U-boot and kernel.

Pin-mux file used and the booting log are attached. pin-mux file extension i.e. 'am571x_minimal.pinmux' was changed to 'am571x_minimal.txt' as upload error occurred.

mux_data.h of U-boot was modified using the files generated with this pin-mux.

core_padconf_array_essential_am571x_idk[] and iodelay_cfg_entry iodelay_cfg_array_am571x_idk[] in mux_data.h of U-boot were modified.

Changes done in DTS are as follows
-------------------------------------------------------
1. am571x-idk.dtsi
Disabled pruss1_eth,&pruss1_mdio in am571x-idk.dtsi.

2. am571x-idk-common.dtsi
Disabled &ipu1, &ipu2

3. am57xx-idk-common.dtsi
Disabled  &pruss_soc_bus1, &pruss_soc_bus2.
Removed &cpsw_emac1, dual_emac in &mac
Removed dual_emac_res_vlan = <1>; in &cpsw_emac0
-------------------------------------------------------

1) Why i'm getting the following error:

Card did not respond to voltage select!

invalid mmc device

(GPIO6_27 and GPIO6_28 corresponding to MMC card are enabled in the pin-mux)

Though this error is shown, EVM boots with the U-boot and kernel in SD-Card.

2) If I do not change the pin-mux of UART3, eth0,I2c, QSPI1, MMC1 etc. Can I make sure that my custom board will boot with this pin-mux, U-boot and kernel ?

3) Which all peripherals do I need to disable other than these in the DTS?

regards,

Anupama(Please visit the site to view this file)

Part Number: AM6548

Hi Experts,

Could you please let me know the clock source setting for Cortex-A53 and Cortex-R5F?
Is it possible to utilize completely separated clock source for them?
and also is it possible to use the same clock source for both?

Thank you for your check.
Best regards,
HItoshi

Part Number: AM6548

Hi Experts,

Is it possible to access to the same addresses in the shard memory from the different OSs?
I plan to utilize RT-Linux and Non-OS program.

Thank you for your kind check.
Best regards,
HItoshi

Part Number: TMS320C6678

Hi,

power solution:LM10011SD+TPS56121DQPT

The customer bought TMS320C6678ACYPA and TMS320C6678CYPA. They are different in silicon version. But the customer found the Power consumption are different with the same programme and hardware design. The current in TMS320C6678CYPA board is 200MA more than TMS320C6678ACYPA. Is that related to silicon version?

I have checked the errata. But there is nothing with Power consumption difference between silicon 1.0 and silicon 2.0.