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AM3358: Debug UART error

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Part Number: AM3358

Hi Team,

I received the following request , could you assist?

#########################################################################################

We are having trouble running a card we built using the AM3358 CPU from the TI Sitara family.

The debug UART of the card continuously receives 0xC2 information. This information corresponds to an error code. However, we could not find any documents etc. Can you help me with this?

#########################################################################################


RTOS/TDA2PXEVM: SurroundView 3D usecase - The texture of the car's 3D model is displayed only in black and white from any color

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Part Number: TDA2PXEVM

Tool/software: TI-RTOS

Hi Shashank,

Below are few new questions from the Customer:

  1. The texture of the car's 3D model is displayed only in black and white from any color. Would you please modify to display the original bmp texture color?
  2. It can be found from all released version. When found first time, Samsung thought original Car’s colors are grey. But it’s not.
  3. In the case of sedan model in release folder, original texture is Red. And when applying other car model, it also displays in black and white.

Thanks,

Simo

TMS320C6748: EDMA3

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Part Number: TMS320C6748

Finally got around to trying QDMA.  Didn't work :(

My scheme is as follows;

Use QDMA channel 0 to read from a 16-bit GPIO port 16 times and save the readings in an array of 16-bit words.

After POR, I set it up as follows:

// PaRAM Block

#define PaRAM_START 0x01c04000
#define PaRAM_SET_0 0x4000
#define PaRAM_SET_1 (PaRAM_SET_0 + 32)
#define PaRAM_SET_2 (PaRAM_SET_1 + 32)
#define RF_IN (SOC_GPIO_0_REGS + 0x70)
#define NO_LINK 0XFFFF

#define QCHMAP0 0x01c00200
#define QER 0x01c01080
#define QEER 0x01c01084
#define QEECR 0x01c01088
#define QEESR 0x01c0108c

#define IER 0x01c01050
#define IECR 0x01c01058
#define IESR 0x01c01060
#define IPR 0x01c01068
#define ICR 0x01c01070
#define RFDMA_READY (HWREG(IPR) & 0x00000001)

struct __attribute__((__packed__)) T_PaRAM {
// keep declaration order below!
uint32 opt;
uint32 src;
uint16 acnt;
uint16 bcnt;
uint32 dst;
uint16 srcbidx;
uint16 dstbidx;
uint16 link;
uint16 bcntrld;
uint16 srccidx;
uint16 dstcidx;
uint16 ccnt;
uint16 rsvd;
};

int16 RF_READINGS[16];

#pragma LOCATION(data_PaRAM, PaRAM_START)
struct __attribute__((__packed__)) T_PaRAM data_PaRAM;
//=============================================================================

bool QDMA_Done() {
return (RFDMA_READY);
}

//=============================================================================

void InitQDMA() {


int i;
for (i=0;i<16;i++) {
RF_READINGS[i] = 0;
}

//enable QDMA Ch 0
HWREG(QEESR) = 0x00000001;
//clear interrupt status
HWREG(ICR) = 0x00000001;
//set interrupt enable
HWREG(IESR) = 0x00000001;
// initialize PaRAM Set 0
data_PaRAM.src = RF_IN;
data_PaRAM.acnt = 2;
data_PaRAM.bcnt = 16;
data_PaRAM.srcbidx = 0;
data_PaRAM.dstbidx = 2;
data_PaRAM.bcntrld = 0;
data_PaRAM.srccidx = 0;
data_PaRAM.dstcidx = 0;
data_PaRAM.ccnt = 1;
data_PaRAM.dst = (uint32) &RF_READINGS;
data_PaRAM.link = NO_LINK;
// trigger word; must be the last assignment statement in the function
data_PaRAM.opt = 0x00100008; //TCINTEN=1, STATIC=1
}
Then, in an while(1) loop, I call QDMA_Done() to check the bit 0 of IPR.  If it's set, I process the data.  Then, InitQDMA() is called to repeat the procedure.  It does not seem to work - no data transfer observed.  What seems to be missing or incorrect?

PROCESSOR-SDK-AM65X: The SW7 warm reset button does not reset the IDK EVM and causes the system to hang

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Part Number: PROCESSOR-SDK-AM65X

Hello,

Related to the question posted here: https://e2e.ti.com/support/processors/f/791/t/795134?tisearch=e2e-sitesearch&keymatch=PROCESSOR-SDK-K2H

It does not appear that a follow up was ever posted on that.

Is there any update on this issue?

We are looking into changes that need to be made to support booting from eMMC and from MMC/SD (as well as other modes, but primarily those 2).

Thank you,

Christyan Brown

The SW7 warm reset button does not reset the IDK EVM and causes the system to hang

TMS320C6657: SSH Support

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Part Number: TMS320C6657

I have an existing application written for the C665x family DSP that uses telnet. I would like to convert this application to use SSH instead. Looking through the options in Code Composer Studio and documentation online, I haven't found any indication that you offer an SSH library. If this correct, or is there something that I missed?

Alternatively, what are my options for adding SSH support? Are there any third party libraries that you recommend?

AM3358: Device tree file enables some pull-ups (or pull-downs) on pins that already has external pull-ups connected to them

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Part Number: AM3358

Hello Support,

1. Why does the am335x-bone-common.dtsi file for the BBB initialize the MDIO_DATA with its internal pull-up enabled knowing that an external 1.5K pull-up resistor (R119) is already connected to the node where MDIO_DATA is connected? 

The initialization we found is the following:

AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */

 

And the schematic shows the following:

...and same happens with other interfaces, for example, the MMC0 interface (micro-sd) where all the data bus pins have external 10K pull-ups resistors and, however, the device tree enables all the internal pull-ups for those pins:

pinctrl-single,pins = <
AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spio0_cs1.gpio0_6 */
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */
>;

2. For the same interface (MMC0 interface micro-sd), since the CMD pin for a micro-sd card is always an input.... why does the MMC0_CMD pin is not initialized as an output pin in the dtsi file?

AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */

Thanks in advance,

TDA2SX: Angle Finding radar VSDK use case?

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Part Number: TDA2SX

How to customize use case with our angle finding technique for cascade TDA2 EVM? Is modifying the beam forming use case the right place to start? Is there a better choice use case for angle finding or maybe we should look at creating a new custom use case?

AM5726: Out-of-order packets on PRU ethernet ports

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Part Number: AM5726

Hi,

We are using AM5726 in one of our products.

We are using the PRU ethernet driver corresponding to Processor SDK for Linux RT: 04_03_00_05.

We have basic sanity tests for ethernet ports.

Our test is pretty simple: We use a loopback stub on the ethernet port and send custom ethernet packets at close to line rate (96Mbps) and we check if all packets are received and in-order.

In our tests, we are observing we would receive out-of-order packets (of the order of 3 to 9 packets out of 666 packets sent) on the PRU ethernet ports.

I would like to understand a few things:

1. Is this out-of-order packet reception behavior expected? I understand there are multiple Rx queues for the PRU ethernet.

Was this issue reported by some other customer and was fixed in the some later releases?

2. If there a way to guarantee in-order delivery of packets? 

In one of your documentation, I found that we can use the taskset command to set the CPU affinity of the IRQ thread to a single CPU.This seems to ensure that we get in-order packets. But sometimes, we have observed frame errors on the PRU ethernet ports. It looks like maybe the Rx queues are getting full before the driver can acknowledge all the packets. 

Do you see any other side effects of limiting the IRQ thread affinity to a single CPU?

3. We would prefer to create the kernel IRQ thread and have its affinity set to a single CPU in the driver itself rather than use the taskset command?

Can you please suggest ways to accomplish that in the driver?

Thanks,

Mukul


DRA72XEVM: Unable to get correct video displayed during channel switching

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Part Number: DRA72XEVM

Hi TI Forum,

We are trying to run below usecase on our custom board having TDA2xx SoC. We are using Vision SDK 3.0.7

Capture -> Dup -> VPE -> Merge

Dup -> VPE_D2 -> Alg_DmaSwMs -> Merge

Merge -> Display

We have connected 4 cameras. In the above usecase we are trying to display Mosaic view(4 camera display - number of windows set to 4) in Channel 0 and Single channel display in Channel 1,2,3,4

We are using below API to switch between channels 0 to 4.

System_linkControl(displayID,
DISPLAY_LINK_CMD_SWITCH_CH,
&params,
sizeof(params),
TRUE);

For channel - 0 we are getting the correct video of all the 4 cameras in Mosaic splitted into 4 windows. We are using below API to set the Mosaic properties.

But when we switch to channel-1,2,3,4 video is not proper seems to be interleaved and distorted. It looks like the video output format is altered by Merge[0].

Expected output when switch to Channel 1 should display from Camera1, Channel 2 should display from Camera2, Channel 3 should display from Camera3, and Channel 4 should display from Camera4 all videos correctly but is displayed distorted and interleaved.

Void ChainsCommon_SetAlgDmaSwMsPrm(
AlgorithmLink_DmaSwMsCreateParams *pPrm,
UInt32 numLvdsCh,
UInt32 channelWidth,
UInt32 channelHeight,
UInt32 channelSpacingHor,
UInt32 channelSpacingVer)


{
UInt32 algId, winId;
UInt32 useLocalEdma;
AlgorithmLink_DmaSwMsLayoutWinInfo *pWinInfo;

useLocalEdma = FALSE;
algId = ALGORITHM_LINK_IPU_ALG_DMA_SWMS;

pPrm->baseClassCreate.algId = algId;
pPrm->numOutBuf = 4;
pPrm->useLocalEdma = useLocalEdma;
pPrm->initLayoutParams.numWin = numLvdsCh; //numCh;

pPrm->maxOutBufWidth = 640;
pPrm->maxOutBufHeight = 480;

for(winId=0; winId<pPrm->initLayoutParams.numWin; winId++)
{
pWinInfo = &pPrm->initLayoutParams.winInfo[winId];
pWinInfo->chId = winId;
//pWinInfo->chId = 0;
pWinInfo->inStartX = 0;
pWinInfo->inStartY = 0;
pWinInfo->width = channelWidth;
pWinInfo->height = channelHeight;
Vps_printf("Win-ID = %d\n", pWinInfo->chId);
/*
* For 4x4 layout
*/
switch(winId)
{
default:
case 0:
pWinInfo->outStartX = 0;
pWinInfo->outStartY = 0;
break;
case 1:
pWinInfo->outStartX = 320; //winWidth;
pWinInfo->outStartY = 0;
pWinInfo->width = 320/*960*/; //winWidth;
pWinInfo->height = 240/*540*/; //winHeight;
break;
case 2:
pWinInfo->outStartX = 0;
pWinInfo->outStartY = 240; //winHeight;
pWinInfo->width = 320/*960*/; //winWidth;
pWinInfo->height = 240/*540*/; //winHeight;
break;
case 3:
pWinInfo->outStartX = 320; //winWidth;
pWinInfo->outStartY = 240; //winHeight;
pWinInfo->width = 320/*960*/; //winWidth;
pWinInfo->height = 240/*540*/; //winHeight;
break;
}
}

pPrm->initLayoutParams.outBufWidth = pPrm->maxOutBufWidth;
pPrm->initLayoutParams.outBufHeight = pPrm->maxOutBufHeight;

}

Regards,

Sudhi

TDA2EVM5777: Linux, NullSrcDecDisplay UC Frame shift problem

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Part Number: TDA2EVM5777

Hi.

I'm working a project with TDA2EVM5777.

I looked at the NullSrc_Decode_Display Usecase provided by Apps and found that there was a frame shift in the link.

And we found that VPE was cutting the shifted frame.

This image is from the decode link.

You can see that the frame shifted at the top and left.

Parts of the lower and right parts of the original image were shifted and removed.

This image from after the VPE link.

The frame shift is gone, but it is a resized image that has blown away the lower and right parts of the original image.

Is this frame shift normal situation?

What should I do to prevent this frame shift?

I'd like to get the same image as the one entered in NullSrc during the entire link process.

Regards,

Lee.

PROCESSOR-SDK-AM437X: How to config TSC_ADC(ADC0) to support 5-wire TSC

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Part Number: PROCESSOR-SDK-AM437X

Hi,

We designed a custom board to support touchscreen  with 5 general-purpose ADC0 channels.in Am4379. There are only 4 wire TSC in DTS:

&tscadc {
    status = "okay";
    tsc {
         ti,wires = <4>;
         ti,x-plate-resistance = <200>;
         ti,coordinate-readouts = <5>;
         ti,wire-config = <0x01 0x10 0x23 0x32>;
         ti,charge-delay = <0x800>;
   };
   adc {
         ti,adc-channels = <4 5 6 7>;
   };

};
We use 5 inputs (ADC0_AIN0, ADC0_AIN1, ADC0_AIN2,ADC0_AIN3,ADC0_AIN4)  connected to touchscree 5 pins respectively.( Is there an error in Technical_Reference_Manual(Rev_H) that 5-wire TSC with 3 general-purpose ADC channels in 11.1 Page 1794?).

I want to know how to modify the DTS, and how to config kernel with TI touchscreen support. Our SDK is sdk-05.01.00.11. Is there any document about TSC config to reference?

Best Regards,

CCS/AM3352: AM3352 linux system and wince system DDR3 proplem

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Part Number: AM3352

Tool/software: Code Composer Studio

hi  Team:

1. When I use  linux system and wince system ,  DDR2  is  normal

2. when I use  wince system ,  DDR3  is  unnormal,the DDR3 Memory reduced  by 4k in about a second (Linux normal) ,open my device, control panel, system properties, memory, and find that the memory in use has been reduced; why? how to  solve?

3. Usb for wince system, unplug sometimes undetected; WINCE7\public\ oak\drivers\usb\ HCD \usb20\usb2com\cdevice. CPP GetDescriptorD reads dwBytesTransferred's value and wDescriptorSize are not equal, and dwErrorFlags flag is error state, so usb initialization was not successful.  why?  

CCS/TMS320C6678: Polled mode vs Interrupt mode in SRIO

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Part Number: TMS320C6678

Tool/software: Code Composer Studio

Hello.

I want to send and receive Direct I/O packets and Message passing packets between DSP (C6678) and FPGA with 1.25, 2.5, 3.125, and 5 Gbps rates.

Also, I studied SRIO examples.

My questions are:

1- Do "polled mode" and "interrupt mode" affect the link throughput (and link bit rate)? Which of them should I use to achieve maximum throughput?

2- Do both "polled mode" and "interrupt mode" support the Direct I/O packets and Message passing packets?

3- Can I achieve 1.25, 2.5, 3.125, and 5 Gbps rates using only a single core of c6678?

4- Each driver instance needs to configure various CPPI & QMSS parameters before it can be used. These configurations are exposed to the applications as "Application Managed Configuration" and "Driver Managed Configuration". Do both "Application Managed Configuration" and "Driver Managed Configuration" lead to achieve 1.25, 2.5, 3.125, and 5 Gbps rates?

5- Do both "Application Managed Configuration" and "Driver Managed Configuration" support the Direct I/O packets and Message passing packets?

Thank you for your attention.

AM5728: Reference board Sitara AM572x does not boot on default SDK image

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Part Number: AM5728

I have this reference board SItara AM572x Rev 1.2A
I am using  http://software-dl.ti.com/processor-sdk-linux/esd/AM57X/latest/index_FDS.html

I built the kernel, just typing make.
I am flashing the sdcard wit the slightly modified sdcard_create faulty script.

Command (m for help): p
Disk /dev/mmcblk0: 14.6 GiB, 15653142528 bytes, 30572544 sectors
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disklabel type: dos
Disk identifier: 0xee4090c3

Device         Boot  Start      End  Sectors  Size Id Type
/dev/mmcblk0p1 *        63   144584   144522 70.6M  c W95 FAT32 (LBA)
/dev/mmcblk0p2      160650 30572543 30411894 14.5G 83 Linux

Command (m for help): 

All the files seems to be ok on the sdcard

The boot stops:

Trying to boot Linux from eMMC ...
switch to partitions #0, OK
mmc1(part 0) is current device
SD/MMC found on device 1
** No partition table - mmc 1 **
Trying to boot Android from eMMC ...
switch to partitions #0, OK
mmc1(part 0) is current device
mmc - MMC sub system
   
Usage:
mmc info - display info of the current MMC device
mmc read addr blk# cnt
mmc write addr blk# cnt
mmc erase blk# cnt
mmc rescan
mmc part - lists available partition on current mmc device
mmc dev [dev] [part] - show or set current mmc device [partition]
mmc list - lists available devices
mmc hwpartition [args...] - does hardware partitioning
  arguments (sizes in 512-byte blocks):
    [user [enh start cnt] [wrrel {on|off}]] - sets user data area attributes
    [gp1|gp2|gp3|gp4 cnt [enh] [wrrel {on|off}]] - general purpose partition
    [check|set|complete] - mode, complete set partitioning completed
  WARNING: Partitioning is a write-once setting once it is set to complete.
  Power cycling is required to initialize partitions after set to complete.
mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode
 - Set the BOOT_BUS_WIDTH field of the specified device
mmc bootpart-resize <dev> <boot part size MB> <RPMB part size MB>
 - Change sizes of boot and RPMB partitions of specified device
mmc partconf dev [boot_ack boot_partition partition_access]
 - Show or change the bits of the PARTITION_CONFIG field of the specified device
mmc rst-function dev value
 - Change the RST_n_FUNCTION field of the specified device
mmc partconf dev [boot_ack boot_partition partition_access]
 - Show or change the bits of the PARTITION_CONFIG field of the specified device
mmc rst-function dev value
 - Change the RST_n_FUNCTION field of the specified device
   WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.
mmc setdsr <value> - set DSR register value
   
mmc - MMC sub system
   
Usage:
mmc info - display info of the current MMC device
mmc read addr blk# cnt
mmc write addr blk# cnt
mmc erase blk# cnt
mmc rescan
mmc part - lists available partition on current mmc device
mmc dev [dev] [part] - show or set current mmc device [partition]
mmc list - lists available devices
mmc hwpartition [args...] - does hardware partitioning
  arguments (sizes in 512-byte blocks):
    [user [enh start cnt] [wrrel {on|off}]] - sets user data area attributes
    [gp1|gp2|gp3|gp4 cnt [enh] [wrrel {on|off}]] - general purpose partition
    [check|set|complete] - mode, complete set partitioning completed
  WARNING: Partitioning is a write-once setting once it is set to complete.
  Power cycling is required to initialize partitions after set to complete.
mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode
 - Set the BOOT_BUS_WIDTH field of the specified device
mmc bootpart-resize <dev> <boot part size MB> <RPMB part size MB>
 - Change sizes of boot and RPMB partitions of specified device
mmc partconf dev [boot_ack boot_partition partition_access]
 - Show or change the bits of the PARTITION_CONFIG field of the specified device
mmc rst-function dev value
 - Change the RST_n_FUNCTION field of the specified device
   WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.
mmc setdsr <value> - set DSR register value
   
mmc - MMC sub system
   
Usage:
mmc info - display info of the current MMC device
mmc read addr blk# cnt
mmc write addr blk# cnt
mmc erase blk# cnt
mmc rescan
mmc part - lists available partition on current mmc device
mmc dev [dev] [part] - show or set current mmc device [partition]
mmc list - lists available devices
mmc hwpartition [args...] - does hardware partitioning
  arguments (sizes in 512-byte blocks):
    [user [enh start cnt] [wrrel {on|off}]] - sets user data area attributes
    [gp1|gp2|gp3|gp4 cnt [enh] [wrrel {on|off}]] - general purpose partition
    [check|set|complete] - mode, complete set partitioning completed
  WARNING: Partitioning is a write-once setting once it is set to complete.
  Power cycling is required to initialize partitions after set to complete.
mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode
 - Set the BOOT_BUS_WIDTH field of the specified device
mmc bootpart-resize <dev> <boot part size MB> <RPMB part size MB>
 - Change sizes of boot and RPMB partitions of specified device
mmc partconf dev [boot_ack boot_partition partition_access]
 - Show or change the bits of the PARTITION_CONFIG field of the specified device
mmc rst-function dev value
 - Change the RST_n_FUNCTION field of the specified device
   WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.
mmc setdsr <value> - set DSR register value
mmc setdsr <value> - set DSR register value
   
Wrong Image Format for bootm command
ERROR: can't get kernel image!


////////////////  some extra info

=> mmc list
OMAP SD/MMC: 0
OMAP SD/MMC: 1 (eMMC)
=> mmc part
## Unknown partition table type 0
=> mmc info
Device: OMAP SD/MMC
Manufacturer ID: 70
OEM: 100
Name: S1001
Bus Speed: 48000000
Mode : MMC DDR52 (52MHz)
Rd Block Len: 512
MMC version 5.0
High Capacity: Yes
Capacity: 14.6 GiB
Bus Width: 8-bit DDR
Erase Group Size: 512 KiB
HC WP Group Size: 16 MiB
User Capacity: 14.6 GiB
Boot Capacity: 4 MiB ENH
RPMB Capacity: 4 MiB ENH
=> 

What I  am missing.

TMS320C6713B: HPI boot, Readback from L2 RAM fails at temperature over 60 degC.

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Part Number: TMS320C6713B

Hello,
If you know, could you please tell us any cases that are close to my customer's?:
Is it possible to relate the wrong value from the address 0x00000000 and the high temp 60degC ?

- Issue: In the HPI boot Phase3, A Write-Readback test failed.
    - Address: 0x00000000 (Internal RAM L2)
    - Written value: 0x5555AAAA.
    - Read value: Ramdom, other than All-zero and All-1's
- TMS320C6713B.
- HPI boot.
- Failed only in higher temperature, over 60 degC. No failures when under 60 degC.


This time we would like to ask if you know a closer case.

We would like to make a new question if additional data comes.


AM5718: AM5718 The system cannot find the path specified.

AM3352: SOFTCONN flag

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Part Number: AM3352

Hi,

We are implementing a device driver with AM3352 USB controller as the USB host, using VxWorks.

After initialization of USB controller, POWER.SOFTCONN bit is set.

We imagine that it is automatically set by the controller, because our device driver does not set it.

Is this behavior correct?

 Because SOFTCONN bit is set, we are facing a problem that it cannot recognize device disconnection.

Any details on how the USB POWER.SOFTCONN flag could be set automatically ?

There is limited documentation on the USB Core for the AM3352, any help would be greatly appreciated.

Thanks and regards.

TDA3MV: Question about TDA3 VIN MIPI function

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Part Number: TDA3MV

Hi TI,

For the TDA3 VIN  MIPI port, does it can separate the data per input port(each DS90UB936 RIN port connect different camera sensor) deserialized from DS90UB936?

BR

jason_koo

Compiler/AM5718: CPSW ETHERNET ISSUE

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Part Number: AM5718

Tool/software: TI C/C++ Compiler

Hi Sir,

We have developed a custom board for am5718 using ti-processor-sdk-linux-am57xx-evm-05.02.00.10. We are able to completely boot upto root  but we are facing the ethernet problem and the phy is not getting detected and the link is not up as mentioned below and we have also mentioned the configurations we have done inorder to enable the ethernet but it didn't work out. So kindly have a glance at the dts configuration mentioned below and also through the boot log related to the ethernet and suggest how to move further.

   davinci_mdio_pins: pinmux_davinci_mdio_pins {
            pinctrl-single,pins = <
                /* MDIO */
            DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0)                /* mdio_mclk */
            DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0)                  /* mdio_d */

        >;
        };

       davinci_mdio_pins_sleep: pinmux_davinci_mdio_pins_sleep {
        pinctrl-single,pins = <
                /* MDIO reset value */
          
            DRA7XX_CORE_IOPAD(0x363c, PIN_INPUT_PULLDOWN | MUX_MODE7)                /* mdio_mclk */
            DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLDOWN | MUX_MODE7)                  /* mdio_d */

        >;
        };


    cpsw_pins_default: cpsw_pins_default {
         pinctrl-single,pins = <


            DRA7XX_CORE_IOPAD(0x3644, PIN_INPUT | MUX_MODE0) /* RMII_MHZ_50_CLK */
            DRA7XX_CORE_IOPAD(0x367c, PIN_OUTPUT | MUX_MODE1) /*rmii txd0 */
            DRA7XX_CORE_IOPAD(0x3678, PIN_OUTPUT | MUX_MODE1) /* rmii txd1 */
            DRA7XX_CORE_IOPAD(0x3674, PIN_OUTPUT | MUX_MODE1) /*  rmii txen */
            DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT| MUX_MODE1) /*  rmii rxd0 */
            DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT  | MUX_MODE1) /*  rmii rxd1  */
            DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT  | MUX_MODE1) /* rrmii rxer */
            DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE1) /*  rmii rxcrsdv*/

                                         >;

};


    cpsw_pins_sleep: cpsw_pins_sleep {
         pinctrl-single,pins = <



            DRA7XX_CORE_IOPAD(0x3644, PIN_INPUT | MUX_MODE7) /* RMII_MHZ_50_CLK */
            DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE7) /*rmii txd0 */
            DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE7) /* rmii txd1 */
            DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE7) /*  rmii txen */
            DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT| MUX_MODE7) /*  rmii rxd0 */
            DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT  | MUX_MODE7) /*  rmii rxd1  */
            DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT  | MUX_MODE7) /* rrmii rxer */
            DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE7) /*  rmii rxcrsdv*/

                                      >;

};


&mac {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&cpsw_pins_default>;
    pinctrl-1 = <&cpsw_pins_sleep>;
    //dual_emac;
    slaves = <1>;
};


&cpsw_emac0 {
    
                phy_id = <&davinci_mdio>,<9>;
                phy-mode = "rmii";
   
        
};


&davinci_mdio {
       status = "okay";
        pinctrl-names = "default", "sleep";
       pinctrl-0 = <&davinci_mdio_pins>;
       pinctrl-1 = <&davinci_mdio_pins_sleep>;
 
};


Bootlog:-

root@am57xx-evm:~#
root@am57xx-evm:~# dmesg | grep davinci
[    1.800877] davinci_mdio 48485000.mdio: davinci mdio revision 1.6, bus freq 1000000
[    1.808571] davinci_mdio 48485000.mdio: no live phy, scanning all
[    1.815792] davinci_mdio: probe of 48485000.mdio failed with error -5


root@am57xx-evm:~# dmesg | grep phy    
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
[    1.740415] libphy: Fixed MDIO Bus: probed
[    1.808571] davinci_mdio 48485000.mdio: no live phy, scanning all
[   12.575839] libphy: PHY 48485000.mdio:09 not found
[   12.655508] net eth0: phy "48485000.mdio:09" not found on slave 0, err -19


root@am57xx-evm:~# dmesg | grep eth
[    1.847161] cpsw 48484000.ethernet: Detected MACID = 98:5d:ad:9a:0f:fc
[    1.853788] cpsw 48484000.ethernet: initialized cpsw ale version 1.4
[    1.860170] cpsw 48484000.ethernet: ALE Table size 1024
[    1.865443] cpsw 48484000.ethernet: device node lookup for pps timer failed
[    1.872486] cpsw 48484000.ethernet: cpts: overflow check period 500 (jiffies)
[   12.489619] net eth0: initializing cpsw version 1.15 (0)
[   12.655508] net eth0: phy "48485000.mdio:09" not found on slave 0, err -19
[   12.807776] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready


root@am57xx-evm:~# ethtool eth0
Settings for eth0:
        Supports Wake-on: d
        Wake-on: d
        Current message level: 0x00000000 (0)
                               
        Link detected: no


root@am57xx-evm:~# ethtool -S eth0
NIC statistics:
     Good Rx Frames: 0
     Broadcast Rx Frames: 0
     Multicast Rx Frames: 0
     Pause Rx Frames: 0
     Rx CRC Errors: 0
     Rx Align/Code Errors: 0
     Oversize Rx Frames: 0
     Rx Jabbers: 0
     Undersize (Short) Rx Frames: 0
     Rx Fragments: 0
     Rx Octets: 0
     Good Tx Frames: 0
     Broadcast Tx Frames: 0
     Multicast Tx Frames: 0
     Pause Tx Frames: 0
     Deferred Tx Frames: 0
     Collisions: 0
     Single Collision Tx Frames: 0
     Multiple Collision Tx Frames: 0
     Excessive Collisions: 0
     Late Collisions: 0
     Tx Underrun: 0
     Carrier Sense Errors: 0
     Tx Octets: 0
     Rx + Tx 64 Octet Frames: 0
     Rx + Tx 65-127 Octet Frames: 0
     Rx + Tx 128-255 Octet Frames: 0
     Rx + Tx 256-511 Octet Frames: 0
     Rx + Tx 512-1023 Octet Frames: 0
     Rx + Tx 1024-Up Octet Frames: 0
     Net Octets: 0
     Rx Start of Frame Overruns: 0
     Rx Middle of Frame Overruns: 0
     Rx DMA Overruns: 0
     Rx DMA chan 0: head_enqueue: 1
     Rx DMA chan 0: tail_enqueue: 127
     Rx DMA chan 0: pad_enqueue: 0
     Rx DMA chan 0: misqueued: 0
     Rx DMA chan 0: desc_alloc_fail: 0
     Rx DMA chan 0: pad_alloc_fail: 0
     Rx DMA chan 0: runt_receive_buf: 0
     Rx DMA chan 0: runt_transmit_bu: 0
     Rx DMA chan 0: empty_dequeue: 0
     Rx DMA chan 0: busy_dequeue: 0
     Rx DMA chan 0: good_dequeue: 0
     Rx DMA chan 0: requeue: 0
     Rx DMA chan 0: teardown_dequeue: 0
     Tx DMA chan 0: head_enqueue: 0
     Tx DMA chan 0: tail_enqueue: 0
     Tx DMA chan 0: pad_enqueue: 0
     Tx DMA chan 0: misqueued: 0
     Tx DMA chan 0: desc_alloc_fail: 0
     Tx DMA chan 0: pad_alloc_fail: 0
     Tx DMA chan 0: runt_receive_buf: 0
     Tx DMA chan 0: runt_transmit_bu: 0
     Tx DMA chan 0: empty_dequeue: 0
     Tx DMA chan 0: busy_dequeue: 0
     Tx DMA chan 0: good_dequeue: 0
     Tx DMA chan 0: requeue: 0
     Tx DMA chan 0: teardown_dequeue: 0


root@am57xx-evm:~# ifconfig
eth0      Link encap:Ethernet  HWaddr 98:5D:AD:9A:0F:FC  
          inet addr:10.0.0.5  Bcast:10.0.0.255  Mask:255.255.255.0
          UP BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
          Interrupt:93

lo        Link encap:Local Loopback  
          inet addr:127.0.0.1  Mask:255.0.0.0
          inet6 addr: ::1%775872/128 Scope:Host
          UP LOOPBACK RUNNING  MTU:65536  Metric:1
          RX packets:162 errors:0 dropped:0 overruns:0 frame:0
          TX packets:162 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:12300 (12.0 KiB)  TX bytes:12300 (12.0 KiB)



Thanks and Regards,

A.Mounika

AM3358: EHRPWM: what can the B-output do?

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Part Number: AM3358

EHRPWM in AM335x comes with two outputs A and B (e.g. EHRPWM1A is available on a different pin than EHRPWM1B). What I do not understand: what can this second B-output be used for? Does it provide exactly the same signal than the A-output or can it be programmed independently?

In case it can be used independent from an already running A-output: how do I select "B" during programming?

Thanks!

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