Part Number: AM3358

Tool/software: Code Composer Studio

hello,everyone:

       I used QT to design a program to identify a combination of keys.

       For example, Ctrl+1, Ctrl+2, Ctrl+3, Ctrl+4 and so on, the program works normally under Windows and receives the corresponding ASCII characters of 49, 50, 51, 52.

       But in the system designed with am3358 core board, the corresponding ASCII acceptance characters of 40, 59, 92, 93.

       Which reasons may cause the above phenomenon?

                                                               thank you ！

Part Number: AM3352

Hi,

My customer has an issue with booting from SD Card on MMC0 in their custom board.

The board is based on BeagleBone Green(BBG) and customer copied most of design from BBG.
- DDR and circuit
- SD card circuit
- SYSBOOT setting
- etc.

Then customer uses the same SD card with an image which boot successfully on BBG, but it fails on the customer board (nothing booted).
According to customer observation, only mmc_dat0 signal is toggling during boot sequence compared to BBG (other data signals are toggled).
I think MMCSD boot sequence switches from 1bit mode to 4bit mode if SD card is detected.
(all SD card supports 4bit mode)

If customer connects CCS and loads image via JTAG, the code runs properly, so other parts (clock, power supply, DDR, etc.) should be OK.

Is there any reason why SD card boot fails?
Why the mode cannot switch from 1bit mode to 4bit mode?

Thanks and regards,
Koichiro Tashiro

Part Number: TMS320C6678

Hi,

The customer write data to 0x80010000 from FPGA to DSP by SRIO. Then DSP copy data from 0x80010000 to 0x90000000 by memcpy. But the data wrong unless he used CACHE_invL1d() in 0x80010000. His DDR3 is non-cacheable. Please help explain in detail.

Part Number: AM5749

Hi

1) What is the minimum/optimum DDR3 memory required for operating TIDL on two video sources and one video output in AM5749 ?

2)  What is the minimum/optimum eMMC/SDcard memory required for the same ?

Thanks

Bivin

Part Number: BEAGLEBK

Hi,

   I am developing kernel device driver for ADV7381. 

To start with,I compiled the kernel for BBB as per the procedure described here https://www.digikey.com/eewiki/display/linuxonarm/BeagleBone+Black .

After booting linux from SD card in BBB, I connected the i2c bus to my device. I am trying to detect the devices connected to i2c2-bus using i2cdetect -y -r 2 . It detects all the devices on the board like ADV7511, EEPROMs etc. except the device at address 0x20 (address of chip ADV7381). Why could this be?

i2cdetect -y -r 2

       0 1 2  3 4  5  6 7  8 9 a b c d e f

00: -- -- -- -- -- -- -- -- -- -- -- -- --

10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

30: -- -- -- -- -- -- -- -- 38 39 -- -- 3c -- 3e 3f

40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

50: 50 -- -- -- UU UU UU UU -- -- -- -- -- -- -- --

60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --

70: -- -- -- -- -- -- -- --

In above, for example 39 is  address of ADV7511 and 50 of EEPROM. All these are in same board and are connected to same i2c line. I expected ADV7381 to be present at 0x20 address, but it does not get detected.

Please help. 

My kernel version is 4.14.115-bone23.

Part Number: BEAGLEBK

I have a problem configuring IPv6 using NDK for TI-RTOS. Could you point out my mistake or provide a sample code of IPv6 config and socket creation?

I use *.cfg configuration with IPv6 support enabled. This is my code :

#ifdef IPV6_TEST
static void IPv6DADStatus(IP6N Address, unsigned short dev_index, unsigned char Status)
{
    char strIPAddress[40];

    /* Convert the IP Address to String Format. */
    IPv6IPAddressToString(Address, strIPAddress);

    /* Print the status of the address. */
    NIMU_log("IPv6 address: %s on device %d is %s\n", strIPAddress, dev_index,
        (Status == 1) ? "UNIQUE" : "DUPLICATE");

    return;
}
#endif

/* ========================================================================== */
/*                            MAIN                                            */
/* ========================================================================== */
int main()
{
    /* Call board init functions */
    Board_initCfg boardCfg;
    Task_Params taskParams;
    EMAC_HwAttrs_V4 cfg;

    boardCfg = BOARD_INIT_PINMUX_CONFIG |
        BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO;
    Board_init(boardCfg);

    /* Chip configuration MII/RMII selection */
    SOCCtrlCpswPortMacModeSelect(1, ETHERNET_MAC_TYPE_MII);
    SOCCtrlCpswPortMacModeSelect(2, ETHERNET_MAC_TYPE_MII);

    EMAC_socGetInitCfg(0, &cfg);
    cfg.port[0].phy_addr = EMAC_CPSW_PORT0_PHY_ADDR_EVM;
    cfg.port[1].phy_addr = EMAC_CPSW_PORT0_PHY_ADDR_EVM;
    cfg.macModeFlags = EMAC_CPSW_CONFIG_MODEFLG_FULLDUPLEX;
    EMAC_socSetInitCfg(0, &cfg);

#ifdef IPV6_TEST
    llEnter ();
    int status = IPv6InterfaceInit(1, IPv6DADStatus);
    llExit ();

    if (status < 0) {
        NIMU_log("Unable to initialize the IPv6 stack\n");
    }else{
        NIMU_log("initialized IPv6 stack\n");
    }

#endif

    Task_Params_init(&taskParams);
    taskParams.priority = 3;
    taskParams.stackSize = 0x2400;
    taskParams.instance->name = "SOC-recive";
    Task_create(socket_recive_test, &taskParams, NULL);

    Task_Params_init(&taskParams);
    taskParams.priority = 1;
    taskParams.stackSize = 0x2400;
    taskParams.instance->name = "SOC-send";
    Task_create(socket_send_test, &taskParams, NULL);

    NIMUDeviceTable[nimu_device_index++].init =  &CpswEmacInit ;
    NIMUDeviceTable[nimu_device_index].init =  NULL ;

    BIOS_start();

    return -1;
}

When i run it i get : CortxA8: Unhandled ADP_Stopped exception 0x800FCC38

Its based on a  MINU_BasicExample from the PDK

Part Number: TDA2PXEVM

Hello All,

I'm working on TDA2PX EVM and visionSdk 3.5 version.

I have following usecase:

NetworkRx (A15) -> Decode -> Sync -> Dup -> Alg_Plugin1 (DSP1) -> Merge

Dup -> Alg_Plugin2 (DSP2) -> Merge

Dup -> Alg_Plugin3 (DSP1)

Merge -> Sync_1 -> DssM2mWb -> Display_Video

CANLink (IPU1_0)

ssdOverlayLink (IPU1_0) -> Display_Grpx

I used Merge link to merge output of two Alg_plugins and sync link to synchronize them. But I get black screen as a output and frame drop in Alg_plugin1(processing of Alg_plugin1 & Alg_plugin2 is commented). I used DSS link as I want split view at the output.

Attached is my usecase stat log:

(Please visit the site to view this file)

Can you please suggest solution so that I wont get frame drop ?

Part Number: DRA76P

hi all,

i load visionSDK IPU2 firmware by bootloader, but when i run app.out, A15 can not communicate with IPU2. log as following:

ASSERT (system_ipc.c|System_ipcInit|119)
 [HOST] [HOST  ]     15.845604 s:  SYSTEM: System A15 Init in progress !!!
 [HOST] [HOST  ]     15.845604 s: System_waitAppInitComplete() IN!!
 [HOST] [HOST  ]     15.845635 s: System_waitAppInitComplete() OUT!!
 [HOST] [HOST  ]     15.845665 s:  SYSTEM: IPC: Init in progress !!!
 [HOST] [HOST  ]     15.845665 s:  SYSTEM: IPC: Notify init in progress !!!
 [HOST] [HOST  ]     15.845757 s:  SYSTEM: IPC: [IPU2] socket bind failed (Invalid argument, 22) !!!
 [HOST] [HOST  ]     15.845757 s:  SYSTEM: IPC: [IPU2] Notify RX channel create failed (endpoint = 81) !!!

then i follow the visionSDK code, i found that IPU2 connet to A15 IPC thread was blocked in the following code:

Part Number: AM5728

We developed and tested am5728 based custom board using linux sdk 03.02 for processing 2 videos of 1024*768 resolution and 1 video of 720*576 resolution . it worked fine for few weeks and suddenly the system is getting hanged with the attached errors on terminal.kindly help us with the issue.(Please visit the site to view this file)

Part Number: TDA2PXEVM

Hello All,

I'm working on TDA2PX and visionSDK 3.5 version.

I want to create Alg_plugin which receives inputs (System_VideoFrameBuffer type) from 2 Alg_plugins, processes it and gives composite output.

I have set "numInputQUsed " to 2, also done changes for composite buffer in plugin create function. I also have done changes in usecase generation tool and generated usecase successfully.

What more changes  I need to do to receive 2 System_VideoFrameBuffer type inputs in the plugin process function ?

Can you please suggest any existing plugin for reference?

Best regards,

Megha

Part Number: AM5728

Tool/software: Linux

We are working with custom board with emmc as only boot device. We are tring to increase cma by entering the following commands in uboot terminal:

=>setenv optargs cma=256MiB.

=>saveenv

But the saveenv is not working.It returns bad or no device error.

I used uEnv.txt for setting up cma but it too did not work.

I checked the cma using cat /cmd/procline after the boot.

How can i hardcode or set the cma default to 256MiB in uboot or kernel.

regards,

Marka

Part Number: AM3358

Hi.

I made designed PCB with AM3358 and TPS65910.

But in booting sequence, there is no 'C' characters output in UART.

I checked the voltages of each power rail and power sequence. And it looks like there is no problem.

24MHz clock did oscilate(well, it was distorted a little...), and 32.768kHz clock didn't oscilate.(RTC clock disabled by default at reset release time, right?)

So I checked with JTAG and I got messege as below.

-----[An error has occurred and this utility has aborted]--------------------

This error is generated by TI's USCIF driver or utilities.

The value is '-233' (0xffffff17).
The title is 'SC_ERR_PATH_BROKEN'.

The explanation is:
The JTAG IR and DR scan-paths cannot circulate bits, they may be broken.
An attempt to scan the JTAG scan-path has failed.
The target's JTAG scan-path appears to be broken
with a stuck-at-ones or stuck-at-zero fault.

Anyone help me what should I check more?

Part Number: TMS320C5535

Hello,

we have the following system which works with synchronous clocks. One AIC3204 is the i2s master of the whole system and generates the clocks for all i2s slaves. The c5535 just loop through the audio data at the moment. The audio transfers work, but sometimes the audio is scrambled after power on. When we reinit the codec and the dsp i2s and dma, scrambling dissappears. What could be the reason for this scrambling?!

(Please visit the site to view this file)

The init procedure of AIC3204 is as follows. The only difference in initialization of master or slave is the register 27 in page 0 (marked in red).

CSL_Status AIC3254_Init(Bool master)
{
CSL_Status result = CSL_SOK;

result = AIC3254_Write(0, 0); // write 0 to page register to select page 0
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(1, 1); // reset codec
if (result != CSL_SOK)
{
return result;
}

/* Select the PLL input and CODEC_CLKIN */
/* PLL input is assumed as 12MHz */
result = AIC3254_Write(4, 0x03);
if (result != CSL_SOK)
{
return result;
}

/*
PLL_CLK = (PLL_CLKIN * R * J.D)/P
DAC_FS = PLL_CLK/(NDAC * MDAC * DOSR)
ADC_FS = PLL_CLK/(NADC * MADC * AOSR)
DAC_CLK = PLL_CLK/NDAC
BCLK = DAC_CLK/BDIV_CLKIN

DAC_FS, BCLK:
16 kHz: P=1, R=1, J=7, D=1754 (0x6da)
NDAC=6, MDAC=7, DOSR=128
BCLK = 28
PLL_CLK = (12e6 * 1 * 7.1754)/1 = 86104800
DAC_FS = PLL_CLK/(6 * 7 * 128) = 16016.52
BCLK = PLL_CLK/NDAC/BCLK = 28701600/2/28 = 512528.57
ADC_FS:
16 kHz: P=1, R=1, J=7, D=1754 (0x6da)
NADC=6, MADC=7, AOSR=128
ADC_FS = PLL_CLK/(2 * 7 * 128) = 16016.52
*/

// Power up the PLL and set P = 1 & R = 1
result = AIC3254_Write(5, 0x91); // 16khz
if (result != CSL_SOK)
{
return result;
}

// Set J value to 7
result = AIC3254_Write(6, 0x07); // 16khz
if (result != CSL_SOK)
{
return result;
}

//
// CODEC_CLKIN = 12MHz *(R * J.D)/P
//

// Set D value(MSB) = 0x06
result = AIC3254_Write(7, 0x6); // 16khz
if (result != CSL_SOK)
{
return result;
}

// Set D value(LSB) = 0xda
result = AIC3254_Write(8, 0xda); // 16khz
if (result != CSL_SOK)
{
return result;
}

// Set NDAC to 6 - this along with BCLK N configures BCLK
result = AIC3254_Write(11, 0x86); // 16khz
if (result != CSL_SOK)
{
return result;
}

// Set MDAC to 7
result = AIC3254_Write(12, 0x87); // 16khz
if (result != CSL_SOK)
{
return result;
}

//
// DAC_FS = (12MHz *(R * J.D)/P)/(NDAC * MDAC * DOSR)
//

/* Set DAC OSR MSB value to 0 */
result = AIC3254_Write(13, 0x0);
if (result != CSL_SOK)
{
return result;
}

// Set DAC OSR LSB value to 128
// This generates the DAC_FS = 16KHz
result = AIC3254_Write(14, 128); // 16khz
if (result != CSL_SOK)
{
return result;
}

//
// BCLK = (12MHz *(R * J.D)/P)/(NDAC * BCLK N)
//
// Set BCLK N value to 28
// This along with NDAC generates the BCLK = 512 kHz
// BCLK = (12MHz *(R * J.D)/P)/(NDAC * BCLK N)
result = AIC3254_Write(30, 0x9C); // 16khz
if (result != CSL_SOK)
{
return result;
}

// Set ADC_FS to 16 kHZ

// Set NADC to 6
result = AIC3254_Write(18, 0x86); // 16khz
if (result != CSL_SOK)
{
return result;
}

// Set MADC to 7
result = AIC3254_Write(19, 0x87); // 16khz
if (result != CSL_SOK)
{
return result;
}

// Set ADC OSR LSB value to 128
// This generates the ADC_FS = 16KHz
// ADC_FS = (12MHz *(R * J.D)/P)/(NADC * MADC * AOSR)
result = AIC3254_Write(20, 128); // 16khz
if (result != CSL_SOK)
{
return result;
}

if (master == TRUE)
{
result = AIC3254_Write(27,0xd); // BCLK and WCLK is set as op to AIC3254(Master)
if (result != CSL_SOK)
{
return result;
}
}

result = AIC3254_Write(0, 1); // select page 1
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(51, 0x48); // power up Mic Bias using LDO-IN
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(1, 0x8); // Disable crude AVDD generation from DVDD
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(2, 1); // Enable Analog Blocks and internal LDO
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(20, 0); // Depop reg R=6K,t=8RC(2.256ms),ramp time=0ms
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(14, 0x8); // LDAC AFIR routed to LOL
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(15, 0x8); // RDAC AFIR routed to LOR
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(52, 0xC0); // Route IN1L to LEFT_P with 40K input impedance
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(54, 0xC0); // Route Common Mode to LEFT_M with impedance of 40K
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(55, 0xC0); // Route IN1R to RIGHT_P with 40K input impedance
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(57, 0xC0); // Route Common Mode to RIGHT_M with impedance of 40K
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(59, 0x00); // Unmute Left MICPGA, Gain = 0 dB
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(60, 0x00); // Unmute Right MICPGA, Gain = 0 dB
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(0, 0); // write 0 to page register to select page 0
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(86, 0x90); // Enable LEFT AGC, target level -8dBFs
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(94, 0x90); // Enable RIGHT AGC, target level -8dBFs
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(64, 0x2); // DAC left vol=right vol
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(63, 0xd4); // DAC power up left, right data paths and set channel
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(64, 0xc); // DAC mute
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(0, 1); // select page 1
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(18, 0); // unmute LOL, 0dB gain
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(19, 0); // unmute LOR, 0dB gain
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(9, 0x0C); // power up LOL, LOR
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(0, 0x0); // select page 0
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(64, 0x2); // unmute DAC with right vol=left vol
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(65, 0); // set DAC gain to 0dB
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(66, 0); // set DAC gain to 0dB
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(81, 0xc0); // Powerup left and right ADC
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(82, 0x00); // Unmute left and right ADC
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(83, 0); // Set left ADC Gain to 0dB
if (result != CSL_SOK)
{
return result;
}

result = AIC3254_Write(84, 0); // Set right ADC Gain to 0dB
if (result != CSL_SOK)
{
return result;
}

return result;
}

Initialization of C5535 i2s is as follows:

CSL_Status I2sInit(void)
{
CSL_Status status;
I2S_Config hwConfig;

hI2sLoc->configured = false;

/* Set the value for the configure structure */
hwConfig.dataFormat = I2S_DATAFORMAT_LJUST;
hwConfig.dataType = I2S_STEREO_ENABLE;
hwConfig.loopBackMode = I2S_LOOPBACK_DISABLE;
hwConfig.fsPol = I2S_FSPOL_LOW; // I2S_FSPOL_HIGH
hwConfig.clkPol = I2S_RISING_EDGE; // I2S_FALLING_EDGE
hwConfig.datadelay = I2S_DATADELAY_ONEBIT;
hwConfig.datapack = I2S_DATAPACK_ENABLE;
hwConfig.signext = I2S_SIGNEXT_DISABLE;
hwConfig.wordLen = I2S_WORDLEN_16;
hwConfig.i2sMode = I2S_SLAVE;
hwConfig.clkDiv = I2S_CLKDIV2; // don't care for slave mode
hwConfig.fsDiv = I2S_FSDIV32; // don't care for slave mode
hwConfig.FError = I2S_FSERROR_DISABLE;
hwConfig.OuError = I2S_OUERROR_DISABLE;

/* Configure hardware registers */
status = I2S_setup(hI2sLoc, &hwConfig);
if (status != CSL_SOK)
{
printf("Setup I2S Loc Module failed\n");
return (status);
}

hI2sRem->configured = false;

/* Set the value for the configure structure */
hwConfig.dataFormat = I2S_DATAFORMAT_LJUST;
hwConfig.dataType = I2S_STEREO_ENABLE;
hwConfig.loopBackMode = I2S_LOOPBACK_DISABLE;
hwConfig.fsPol = I2S_FSPOL_LOW; // I2S_FSPOL_HIGH
hwConfig.clkPol = I2S_RISING_EDGE; // I2S_FALLING_EDGE
hwConfig.datadelay = I2S_DATADELAY_ONEBIT;
hwConfig.datapack = I2S_DATAPACK_ENABLE;
hwConfig.signext = I2S_SIGNEXT_DISABLE;
hwConfig.wordLen = I2S_WORDLEN_16;
hwConfig.i2sMode = I2S_SLAVE;
hwConfig.clkDiv = I2S_CLKDIV2; // don't care for slave mode
hwConfig.fsDiv = I2S_FSDIV32; // don't care for slave mode
hwConfig.FError = I2S_FSERROR_DISABLE;
hwConfig.OuError = I2S_OUERROR_DISABLE;

/* Configure hardware registers */
status = I2S_setup(hI2sRem, &hwConfig);
if (status != CSL_SOK)
{
printf("Setup I2S Rem failed\n");
return (status);
}

return CSL_SOK;

}

I2s WCLK and BCLK look as follows:

The peaks at the BCLK occur due to not connected ground on oscilloscope.

I2s WCLK and Data:

I2s BCLK and Data:

We don't know if the initialization of the aic3204 and c5535 i2s is correct and match each other. We took them out of example code from ti. It would be fine if you could take a look at the init procedures and the screenshots. Perhaps you can see the reason for the scrambled sound?! As already mentioned, scrambling only appears sporadic after init of codec and c5535 i2s. When we do a reinit, it dissappears.

Thanks in advance and have a nice day

Marc

Part Number: TDA2E

Hello,

I have a TDA2 board(MMWCAS-DSP-EVM) which TI has confirmed is same as TDA2 EVM. So i compiled the PROCESSOR_SDK_RADAR_03_07_00_00 for usecase tda2xx_cascade_bios_radar and than trying to run this test case on the board but i cannot see any thing on the network or on the Tera Term console. 

what i can see is that on Serial port the use case ask me prompt for to enter Radar Use case to run and than ask further details regarding the details of the testcase and than exit without giving further indication. Is this expected behavior?

On Console logs i can see following information about board and SW

[IPU1-0] 3.298969 s: Vision SDK Version : [REL_VISION_SDK_03_07_00_00]
[IPU1-0] 3.299060 s: FVID2 Version : [FVID_02_01_00_01]
[IPU1-0] 3.299121 s: BSP Version : [PDK_01_10_03_xx]
[IPU1-0] 3.299182 s: Platform : [EVM]
[IPU1-0] 3.299243 s: SOC : [TDA2XX]
[IPU1-0] 3.299304 s: SOC Revision : [ES2.0]
[IPU1-0] 3.299396 s: Board Detected : [TDA2XX CASCADE RADAR]
[IPU1-0] 3.299487 s: Base Board Revision : [REV E]
[IPU1-0] 3.299548 s: Daughter Card Revision: [REV A]

Also before prompting for next run it terminates with below message , it mentions Display Type as  HDMI even though we don't have any display.

[IPU1-0] 4.309125 s: Current System Settings,
[IPU1-0] 4.309186 s: ========================
[IPU1-0] 4.309217 s: Display Type : HDMI 1920x1080 @ 60fps
[IPU1-0] 4.309308 s: My IP address for interface 1 : 0.0.0.0
[IPU1-0] 4.309369 s: My IP address for interface 2 : 0.0.0.0
[IPU1-0] 4.309461 s:
[IPU1-0] 4.309491 s: ============
[IPU1-0] 4.309552 s: Usecase Menu
[IPU1-0] 4.309583 s: ============

I am attaching the complete logs of multiple attempt with various combination (like trying 2nd stage FFT on EVE or DSP and getting logs on TCP/IP or TFDTP) except to run 9: Cascade Radar (4 AWR1243) Capture + Null (TDA2xx Only) (NetworkLogs.txt)

Can some one please comment if the below attached Serials logs are ok and what i am expected to see? Also why i don't see any activity of TCP/IP packet on network ?

In next step i will also run the corresponding use case Matlab file but before that i wanted to just see if i can see any activity on network interface.

Br

Deepak Joshi

(Please visit the site to view this file)

Tool/software: TI C/C++ Compiler

Hello,

I'm received latest Processor SDK RTOS Automotive for J7 device family version 06_00_00_00 (TDA4VM).

And when build error occurred.

$ cd vision_apps

$ make vision_apps

Build error log is like below.

app_mem_linux_cmem_proxy.c file cannot find  #include <ti/cmem.h> header file.

build config is like this. (./tiovx/build_flags.mak)

how to modify & resolve this error??

# Build for SoC
BUILD_TARGET_MODE?=yes
# Build for x86 PC
BUILD_EMULATION_MODE?=no
# valid values: X86 x86_64 all
BUILD_EMULATION_ARCH?=x86_64

# valid values: release debug all
PROFILE?=release

# Applied to target mode only
BUILD_LINUX_A72?=yes
# Applied to target mode only
BUILD_VLAB?=no

==========================================================================================================================

[GCC] Compiling C99 app_mem_sysbios.c
Linking /home/jukyeong1.kim/PSDK_06_00_00_00/psdk_rtos_auto_j7_06_00_00_00/vision_apps/out/J7/A72/SYSBIOS/release/libapp_utils_mem.a
[C6X] Compiling C app_mem_sysbios.c
Linking /home/jukyeong1.kim/PSDK_06_00_00_00/psdk_rtos_auto_j7_06_00_00_00/vision_apps/out/J7/C66/SYSBIOS/release/app_utils_mem.lib
  ==>  new archive '/home/jukyeong1.kim/PSDK_06_00_00_00/psdk_rtos_auto_j7_06_00_00_00/vision_apps/out/J7/C66/SYSBIOS/release/app_utils_mem.lib'
  ==>  building archive '/home/jukyeong1.kim/PSDK_06_00_00_00/psdk_rtos_auto_j7_06_00_00_00/vision_apps/out/J7/C66/SYSBIOS/release/app_utils_mem.lib'
[C7X] Compiling C app_mem_sysbios.c
Linking /home/jukyeong1.kim/PSDK_06_00_00_00/psdk_rtos_auto_j7_06_00_00_00/vision_apps/out/J7/C71/SYSBIOS/release/app_utils_mem.lib
  ==>  new archive '/home/jukyeong1.kim/PSDK_06_00_00_00/psdk_rtos_auto_j7_06_00_00_00/vision_apps/out/J7/C71/SYSBIOS/release/app_utils_mem.lib'
  ==>  building archive '/home/jukyeong1.kim/PSDK_06_00_00_00/psdk_rtos_auto_j7_06_00_00_00/vision_apps/out/J7/C71/SYSBIOS/release/app_utils_mem.lib'
[GCC] Compiling C99 app_mem_linux_cmem_proxy.c
/home/jukyeong1.kim/PSDK_06_00_00_00/psdk_rtos_auto_j7_06_00_00_00/vision_apps/utils/mem/src/app_mem_linux_cmem_proxy.c:71:10: fatal error: ti/cmem.h: No such file or directory
 #include <ti/cmem.h>
          ^~~~~~~~~~~
compilation terminated.
concerto/finale.mak:304: recipe for target '/home/jukyeong1.kim/PSDK_06_00_00_00/psdk_rtos_auto_j7_06_00_00_00/vision_apps/out/J7/A72/LINUX/release/module/utils.mem.src/app_mem_linux_cmem_proxy.o' failed
make: *** [/home/jukyeong1.kim/PSDK_06_00_00_00/psdk_rtos_auto_j7_06_00_00_00/vision_apps/out/J7/A72/LINUX/release/module/utils.mem.src/app_mem_linux_cmem_proxy.o] Error 1

==========================================================================================================================

Thanks & regard.

Jukyeong Kim

Part Number: AM5728

Hi all,

my platform:
AM5729 on BeagleBoard-X15
bios_6_75_02_00 running on both cores ARM Cortex-A15 core 0 and DSP C66x core 0
processor_sdk_rtos_am57xx_5_03_00_07
pdk_am57xx_1_0_14
ipc_3_50_03_05
CCS 7.2.00013 on Win10

I'm trying to use static allocated messages to transfer message from ARM core to DSP core, but any static allocated message causes program crash when it is passed to MessageQ_put function. I don't know if I use static messages correct. Can you please explain what is the correct approach to use static allocated messages?

I used IPC example project:
C:\ti\ipc_3_50_03_05\examples\AM572X_bios_elf\ex02_messageq\

In App.c I created buffer for static messages:
App_Msg buffer[NUM_MSGS] __attribute__ ((section ("OCMC_SHARED")));

In Host.cfg I defined OCMC_SHARED as:
Program.sectMap["OCMC_SHARED"] = "OCMC_RAM1";

And in App.c in App_exec() function I replaced dynamic allocation with assignation from "buffer":
//msg = (App_Msg *)MessageQ_alloc(Module.heapId, Module.msgSize);
msg = buffer + msgCnt;
MessageQ_staticMsgInit((MessageQ_Msg)msg, sizeof(App_Msg));

When that "msg" is passed to MessageQ_put() function, that is few lines below, it causes program crash and the debug jumps to _exit function in syscalls.c or I have got exception with text:
CortexA15_0: Unhandled ADP_Stopped exception

So, what is the correct way how to use static allocated messages?

Part Number: 66AK2H14

Hi everyone,

I red in sprugw0c, DSP corePac documentation, that in case of invalid access an exception its send to CPU. Memory Protection Fault Registers are updated in order to recover information about the occured exception.

My question is does CPU is alerted of its invalid access and know that its access has not been done ?

Also can I manage exceptions ? (with module ti.sysbios.family.c64p.Exception??)

Best Regards,

François

Part Number: TDA3XEVM

Tool/software: Code Composer Studio

I have a TDA3x-15x15 EVM board, and I have run the demo according to the instructions of VisionSDK_UserGuide_TDA3xx. I can build binaries, and load it using CCS. The board is connected to a single camera thru the CSI2 Expansion connector. I can run the ISS use case #1 only (1CH ISS capture + ISS ISP _ ISS LDC+VTNF + Display). Video is displayed on the screen with whatever camera is aiming at. Other use cases failed (run is pending forever). I am wondering for the hardware that I have, can I run other use cases, such as Edge Detection, with or without software changes?

Part Number: PROCESSOR-SDK-AM335X

Hi

 I am trying to connect the Lauterbach with AM335x Starter kit with JTAG. 

When I run the trace32 it shows powerdown. 

All the relevant JTAG Pins are connected to Lauterbach Connector except the VCC. 

My question is do we need to connect the VCC pin of JTAG to Lauterbach. 

Thanks and Regards

Sridevi M 

Part Number: J6EVM5777

Hello Mr/Mrs,

We are trying to make the 3 JAMR3 tlv320aic3106 codecs to be working at the same time. We are facing problems with "jamr3_sound" device-tree definition (dra7xx-jamr3.dtsi).

We are able to manage each one of the 3 codecs, but individually (I mean by generating a different dtb file each time).  To achieve it, what we do it is to change "simple-audio-card,routing" tags and the "sound-dai" of the codec side.

	jamr3_sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-JAMR3";
		simple-audio-card,widgets =
			"Line", "Line Out",
			"Line", "Line In";
		simple-audio-card,routing =
			"Line Out",		"J3A LLOUT",
			"Line Out",		"J3A RLOUT",
			"J3A LINE1L",		"Line In",
			"J3A LINE1R",		"Line In";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&jamr3_sound_master>;
		simple-audio-card,frame-master = <&jamr3_sound_master>;
		simple-audio-card,bitclock-inversion;

		jamr3_sound_master: simple-audio-card,cpu {
			sound-dai = <&mcasp6>;
			system-clock-frequency = <11289600>;
		};

		simple-audio-card,codec {
			sound-dai = <&tlv320aic3106a>;
			clocks = <&atl_clkin1_ck>;
		};
	};

But when we try to define a link between CPU and the 3 codecs at a time, we are not succeeding. We have tried:

• Several dai-links definition:

jamr3_sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-JAMR3-CODECA";
		simple-audio-card,widgets =
			"Line", "Line Out B",
			"Line", "Line In B",
			"Line", "Line Out A",
			"Line", "Line In A";
		simple-audio-card,routing =
			"Line Out A",		"J3A LLOUT",
			"Line Out A",		"J3A RLOUT",
			"J3A LINE1L",		"Line In A",
			"J3A LINE1R",		"Line In A",
			"Line Out B",		"J3B LLOUT",
			"Line Out B",		"J3B RLOUT",
			"J3B LINE1L",		"Line In B",
			"J3B LINE1R",		"Line In B";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&jamr3_sound_master>;
		simple-audio-card,frame-master = <&jamr3_sound_master>;
		simple-audio-card,bitclock-inversion;

		//jamr3_sound_master: simple-audio-card,cpu {
		//	sound-dai = <&mcasp6>;
		//	system-clock-frequency = <11289600>;
		//};
		
		simple-audio-card,dai-link@0{
			simple-audio-card,cpu {
				sound-dai = <&mcasp6>;
			};

			simple-audio-card,codec {
				sound-dai = <&tlv320aic3106a>;
				clocks = <&atl_clkin1_ck>;
			};
		};

		simple-audio-card,dai-link@1{
			simple-audio-card,cpu {
				sound-dai = <&mcasp6>;
			};

			simple-audio-card,codec {
				sound-dai = <&tlv320aic3106b>;
				clocks = <&atl_clkin1_ck>;
			};
		};
	};

• Several codec definition;

jamr3_sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-JAMR3-CODECA";
		simple-audio-card,widgets =
			"Line", "Line Out B",
			"Line", "Line In B",
			"Line", "Line Out A",
			"Line", "Line In A";
		simple-audio-card,routing =
			"Line Out A",		"J3A LLOUT",
			"Line Out A",		"J3A RLOUT",
			"J3A LINE1L",		"Line In A",
			"J3A LINE1R",		"Line In A",
			"Line Out B",		"J3B LLOUT",
			"Line Out B",		"J3B RLOUT",
			"J3B LINE1L",		"Line In B",
			"J3B LINE1R",		"Line In B";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&jamr3_sound_master>;
		simple-audio-card,frame-master = <&jamr3_sound_master>;
		simple-audio-card,bitclock-inversion;

		jamr3_sound_master: simple-audio-card,cpu {
			sound-dai = <&mcasp6>;
			system-clock-frequency = <11289600>;
		};

		simple-audio-card,codec@0 {
			sound-dai = <&tlv320aic3106a>;
			clocks = <&atl_clkin1_ck>;
		};

		simple-audio-card,codec@1 {
			sound-dai = <&tlv320aic3106b>;
			clocks = <&atl_clkin1_ck>;
		};
	};

• Several "cards" definition (if jamr3_sound_b is first defined, DRA7xx-JAMR3_B is mounted. If jamr3_sound_a is first defined, DRA7xx-JAMR3_A is mounted):

jamr3_sound_b {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-JAMR3_B";
		simple-audio-card,widgets =
			"Line", "Line Out",
			"Line", "Line In";
		simple-audio-card,routing =
			"Line Out",		"J3B LLOUT",
			"Line Out",		"J3B RLOUT",
			"J3B LINE1L",		"Line In",
			"J3B LINE1R",		"Line In";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&jamr3_sound_master_b>;
		simple-audio-card,frame-master = <&jamr3_sound_master_b>;
		simple-audio-card,bitclock-inversion;

		jamr3_sound_master_b: simple-audio-card,cpu {
			sound-dai = <&mcasp6>;
			system-clock-frequency = <11289600>;
		};

		simple-audio-card,codec {
			sound-dai = <&tlv320aic3106b>;
			clocks = <&atl_clkin1_ck>;
		};
	};

	jamr3_sound_a {
		compatible = "simple-audio-card";
		simple-audio-card,name = "DRA7xx-JAMR3_A";
		simple-audio-card,widgets =
			"Line", "Line Out",
			"Line", "Line In";
		simple-audio-card,routing =
			"Line Out",		"J3A LLOUT",
			"Line Out",		"J3A RLOUT",
			"J3A LINE1L",		"Line In",
			"J3A LINE1R",		"Line In";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&jamr3_sound_master>;
		simple-audio-card,frame-master = <&jamr3_sound_master>;
		simple-audio-card,bitclock-inversion;

		jamr3_sound_master: simple-audio-card,cpu {
			sound-dai = <&mcasp6>;
			system-clock-frequency = <11289600>;
		};

		simple-audio-card,codec {
			sound-dai = <&tlv320aic3106a>;
			clocks = <&atl_clkin1_ck>;
		};
	};


Anyone could help us to well define the jamr3_sound to be able to manage the 3 codecs at the same time?

Thank you very much!