Part Number:AM5728
HI ,
I am using AM5728 GPEVM, DSP is running on RTOS and A15 core is running on Linux, when I try to access OCMC_RAM1 , OCMC_RAM2 , OCMC_RAM2 form the DSP , the DSP is crashing , and I am getting print like as follows,
[ 357.344655] remoteproc remoteproc2: failed to unmap 201326592/0
[ 357.387105] omap-iommu 40d01000.mmu: iommu fault: da 0x40300000 flags 0x0
[ 357.393927] remoteproc remoteproc2: crash detected in 40800000.dsp: type mmufault
[ 357.401442] omap-iommu 40d01000.mmu: 40d01000.mmu: errs:0x00000002 da:0x40300000 pgd:0xed49d00c *pgd:px00000000
[ 357.411634] remoteproc remoteproc2: handling crash #105 in 40800000.dsp
[ 357.418297] remoteproc remoteproc2: recovering 40800000.dsp
[ 357.426635] remoteproc remoteproc2: failed to unmap 94371840/100663296
[ 357.434522] remoteproc remoteproc2: failed to unmap 201326592/0
[ 357.478513] omap-iommu 40d01000.mmu: iommu fault: da 0x40300000 flags 0x0
[ 357.485334] remoteproc remoteproc2: crash detected in 40800000.dsp: type mmufault.
OCMC addresses are as follows , I tried with all 3 but the result is same.
OCMC_RAM1 40300000 00080000 00000000 00080000 RW X
OCMC_RAM2 40400000 00100000 00000000 00100000 RW X
OCMC_RAM3 40500000 00100000 00000000 00100000 RW X
In the CORE 0 , we have declared char * ptr = 0x40300000 , and trying to a memory copy of 64 K bytes of data from that address to local buffer , but we are getting crash. But when there is no ARM , DSP NO_BOOT mode , we are able to do the memory copy. This is the resource table we are using.
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/*
* ======== rsc_table_vayu_dsp.h ========
*
* Define the resource table entries for all DSP cores. This will be
* incorporated into corresponding base images, and used by the remoteproc
* on the host-side to allocated/reserve resources.
*
*/
#ifndef _RSC_TABLE_VAYU_DSP_H_
#define _RSC_TABLE_VAYU_DSP_H_
#include "rsc_types.h"
/* DSP Memory Map */
#define L4_DRA7XX_BASE 0x4A000000
#define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
#define DSP_PERIPHERAL_L4CFG 0x4A000000
#define L4_PERIPHERAL_L4PER1 0x48000000
#define DSP_PERIPHERAL_L4PER1 0x48000000
#define L4_PERIPHERAL_L4PER2 0x48400000
#define DSP_PERIPHERAL_L4PER2 0x48400000
#define L4_PERIPHERAL_L4PER3 0x48800000
#define DSP_PERIPHERAL_L4PER3 0x48800000
#define L4_PERIPHERAL_L4EMU 0x54000000
#define DSP_PERIPHERAL_L4EMU 0x54000000
#define L3_PERIPHERAL_DMM 0x4E000000
#define DSP_PERIPHERAL_DMM 0x4E000000
#define L3_TILER_MODE_0_1 0x60000000
#define DSP_TILER_MODE_0_1 0x60000000
#define L3_TILER_MODE_2 0x70000000
#define DSP_TILER_MODE_2 0x70000000
#define L3_TILER_MODE_3 0x78000000
#define DSP_TILER_MODE_3 0x78000000
#define DSP_PERIPHERAL_MCASP 0x46000000
#define L3_PERIPHERAL_MCASP 0x46000000
#define DSP_MEM_TEXT 0x95000000
/* Co-locate alongside TILER region for easier flushing */
#define DSP_MEM_IOBUFS 0x80000000
#define DSP_MEM_DATA 0x95100000
#define DSP_MEM_HEAP 0x95A00000
#define DSP_MEM_IPC_DATA 0x9F000000
#define DSP_MEM_IPC_VRING 0xA0000000
#define DSP_MEM_RPMSG_VRING0 0xA0000000
#define DSP_MEM_RPMSG_VRING1 0xA0004000
#define DSP_MEM_VRING_BUFS0 0xA0040000
#define DSP_MEM_VRING_BUFS1 0xA0080000
#define DSP_MEM_IPC_VRING_SIZE SZ_1M
#define DSP_MEM_IPC_DATA_SIZE SZ_1M
#define DSP_MEM_TEXT_SIZE SZ_1M
#define DSP_MEM_DATA_SIZE (SZ_1M * 9)
#define DSP_MEM_HEAP_SIZE (SZ_1M * 4)
#define DSP_MEM_IOBUFS_SIZE (SZ_1M * 90)
#define DSP_CMEM_IOBUFS 0x85000000
#define PHYS_CMEM_IOBUFS 0xA0000000
#define DSP_CMEM_IOBUFS_SIZE (SZ_1M * 192)
/*
* Assign fixed RAM addresses to facilitate a fixed MMU table.
*/
//BWC
#define VAYU_DSP_1
/* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
#if defined (VAYU_DSP_1)
#define PHYS_MEM_IPC_VRING 0x99000000
#elif defined (VAYU_DSP_2)
#define PHYS_MEM_IPC_VRING 0x9F000000
#endif
/* Need to be identical to that of IPU */
#define PHYS_MEM_IOBUFS 0xBA300000
/*
* Sizes of the virtqueues (expressed in number of buffers supported,
* and must be power of 2)
*/
#define DSP_RPMSG_VQ0_SIZE 256
#define DSP_RPMSG_VQ1_SIZE 256
/* flip up bits whose indices represent features we support */
#define RPMSG_DSP_C0_FEATURES 1
struct my_resource_table {
struct resource_table base;
UInt32 offset[18]; /* Should match 'num' in actual definition */
/* rpmsg vdev entry */
struct fw_rsc_vdev rpmsg_vdev;
struct fw_rsc_vdev_vring rpmsg_vring0;
struct fw_rsc_vdev_vring rpmsg_vring1;
/* text carveout entry */
struct fw_rsc_carveout text_cout;
/* data carveout entry */
struct fw_rsc_carveout data_cout;
/* heap carveout entry */
struct fw_rsc_carveout heap_cout;
/* ipcdata carveout entry */
struct fw_rsc_carveout ipcdata_cout;
/* trace entry */
struct fw_rsc_trace trace;
/* devmem entry */
struct fw_rsc_devmem devmem0;
/* devmem entry */
struct fw_rsc_devmem devmem1;
/* devmem entry */
struct fw_rsc_devmem devmem2;
/* devmem entry */
struct fw_rsc_devmem devmem3;
/* devmem entry */
struct fw_rsc_devmem devmem4;
/* devmem entry */
struct fw_rsc_devmem devmem5;
/* devmem entry */
struct fw_rsc_devmem devmem6;
/* devmem entry */
struct fw_rsc_devmem devmem7;
/* devmem entry */
struct fw_rsc_devmem devmem8;
/* devmem entry */
struct fw_rsc_devmem devmem9;
/* devmem entry */
struct fw_rsc_devmem devmem10;
/* devmem entry */
struct fw_rsc_devmem devmem11;
/* devmem entry */
struct fw_rsc_devmem devmem12;
};
//BWC added extern declaration
extern char ti_trace_SysMin_Module_State_0_outbuf__A;
#define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
1, /* we're the first version that implements this */
19, /* number of entries in the table */
0, 0, /* reserved, must be zero */
/* offsets to entries */
{
offsetof(struct my_resource_table, rpmsg_vdev),
offsetof(struct my_resource_table, text_cout),
offsetof(struct my_resource_table, data_cout),
offsetof(struct my_resource_table, heap_cout),
offsetof(struct my_resource_table, ipcdata_cout),
offsetof(struct my_resource_table, trace),
offsetof(struct my_resource_table, devmem0),
offsetof(struct my_resource_table, devmem1),
offsetof(struct my_resource_table, devmem2),
offsetof(struct my_resource_table, devmem3),
offsetof(struct my_resource_table, devmem4),
offsetof(struct my_resource_table, devmem5),
offsetof(struct my_resource_table, devmem6),
offsetof(struct my_resource_table, devmem7),
offsetof(struct my_resource_table, devmem8),
offsetof(struct my_resource_table, devmem9),
offsetof(struct my_resource_table, devmem10),
offsetof(struct my_resource_table, devmem11),
offsetof(struct my_resource_table, devmem12),
},
/* rpmsg vdev entry */
{
TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
/* no config data */
},
/* the two vrings */
{ DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
{ DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },
{
TYPE_CARVEOUT,
DSP_MEM_TEXT, 0,
DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
},
{
TYPE_CARVEOUT,
DSP_MEM_DATA, 0,
DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
},
{
TYPE_CARVEOUT,
DSP_MEM_HEAP, 0,
DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
},
{
TYPE_CARVEOUT,
DSP_MEM_IPC_DATA, 0,
DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
},
{
TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
},
{
TYPE_DEVMEM,
DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
},
{
TYPE_DEVMEM,
DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
},
{
TYPE_DEVMEM,
DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
},
{
TYPE_DEVMEM,
DSP_TILER_MODE_2, L3_TILER_MODE_2,
SZ_128M, 0, 0, "DSP_TILER_MODE_2",
},
{
TYPE_DEVMEM,
DSP_TILER_MODE_3, L3_TILER_MODE_3,
SZ_128M, 0, 0, "DSP_TILER_MODE_3",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
},
{
TYPE_DEVMEM,
DSP_CMEM_IOBUFS, PHYS_CMEM_IOBUFS,
DSP_CMEM_IOBUFS_SIZE, 0, 0, "DSP_CMEM_IOBUFS",
},
{
TYPE_DEVMEM,
DSP_PERIPHERAL_MCASP, L3_PERIPHERAL_MCASP,
SZ_4M, 0, 0, "DSP_PERIPHERAL_MCASP",
},
};
#endif /* _RSC_TABLE_VAYU_DSP_H_ */
Please let me know ,if anything we are missing.
Regards,
R D Nadaf
