Part Number:AM4378

Tool/software: Linux

I have a custom board based on the AM4378 EVM, and I am trying to get it to boot, but it hangs when it tries to load the kernel. U-Boot runs all the way through and has the following output:

U-Boot SPL 2018.01-00558-g8617e02-dirty (Apr 01 2019 - 17:00:43)
Trying to boot from MMC1
SPL: Please implement spl_start_uboot() for your board
SPL: Direct Linux boot not active!

U-Boot 2018.01-00558-g8617e02-dirty (Apr 01 2019 - 17:00:43 -0500)

CPU : AM437X-GP rev 1.2
Model: TI AM437x UTI BOARD
DRAM: 512 MiB
Can't find PMIC:TPS65218_PMIC
NAND: 0 MiB
MMC: OMAP SD/MMC: 0
Net: <ethaddr> not set. Validating first E-fuse MAC
Could not get PHY for cpsw: addr 0
cpsw, usb_ether
Hit any key to stop autobo 0
=>setenv ip_method none
=>setenv bootfile zImage
=>setenv devtype mmc
=>setenv getuenv 'setenv devnum ${mmcdev}; if mmc rescan; then if run loadbootenv; then run importbootenv; fi; fi;'
=>setenv bootcmd 'mmc rescan; run findfdt; run getuenv; setenv devtype mmc; run loadimage; run loadfdt; run args_mmc; bootz ${loadaddr} - ${fdtaddr}'
=>saveenv
Saving Environment to FAT...
writing uboot.env
done
=>boot
709 bytes read in 3 ms (230.5 KiB/s)
Importing environment from mmc0 ...
3639496 bytes read in 203 ms (17.1 MiB/s)
41750 bytes read in 28 ms (1.4 MiB/s)
## Flattened Device Tree blob at 88000000
Booting using the fdt blob at 0x88000000
Loading Device Tree to 8fff2000, end 8ffff315 ... OK

Starting kernel ...

I can see when stepping through the code in CCS that execution gets to the function "rest_init", and stops there - it seems like it's going into some idle loop at that point. I am wondering if it has something to do with the fact that I am not using a PMIC to boot my board currently. I am using TPS74801 LDOs to boot the board, but it seems like U-Boot is expecting a PMIC to be used. Do I have to change some things in U-Boot to let it know that I am not using a PMIC chip, and if so, how do I do that?

Part Number:OMAPL138B-EP

Tool/software: Linux

Hi,

We are using OMAPL138 with linux.We are trying to port ARM2DSP_Integration_ARML138 example code.

With Non OS code we are able to communicate without any issues.

On Linux Arm is able to send interrupts to DSP but  there is an issue in receiving interrupts from DSP.

Program flow is as follows,

//Unlock KICK REGISTERS

 syscfg->KICK0R = KICK0_KEY;
 syscfg->KICK1R = KICK1_KEY

 // Clear all SYSCFG interrupts
    syscfg->CHIPSIG_CLR = 0x1f;

 // Reset AINTC
    aintcreg->ECR1 = 0XF0000000;
    aintcreg->SECR1 = 0xF0000000;

    // Assign SYSCFG Chip1 ISR to SYSCFG Chip1 System Interrupt
    sysISRtbl[29] = (unsigned int *)SYSCFG_chip1_isr;

    // Assign the ISR Table Address to VBR
    aintcreg->VBR = (unsigned int )sysISRtbl;

    // Declare ISR Size (Function Pointer = 4 bytes)
    aintcreg->VSR = 0;

    // Map CHIPSIG1 Interrupts to Channel 2
    aintcreg->CMR7= 0x200;

    // Enable CHIPSIG1 Interrupts
    aintcreg->EISR = 29;

    // Enable IRQ Interrupts
    aintcreg->HIEISR = 1;
    
    // Enable Interrupts
    aintcreg->GER   =   1;
   

 Second bit of CHIPSIG1 register is set  which indicates an event from DSP is received but ISR is not getting called.

Should we provide Physical address or virtual address of isr table in VBR register?

Suggestions would be helpful.

Regards,

sandeep

Part Number:AM3358

Hello，TI

I have three AM335x developed board,(AM335x Starter Kit/MYIR AM3358-J/Self-developed AM3358 board)，there are some problems when I use network port:

• AM335x Starter Kit(TMDSSK3358) have two AR8031 PHY IC, and I use the default android system and connect the port directly to PC  to test dual 1000M network.
  • both eth0 and eth1 can run at 1000M mode, and both eth ping with 65000 byte data length(pattern 0X00) is OK
  • when I use “ping ip -p 0xf0 -s 65000” to test eth1, the probability of time out is about(1~5%) , but eth0 is alway function good.

• Then I run MYIR AM3358-J board(http://www.myir-tech.com/product/myd-am335x-j.htm)  under the same test conditions,  MYIR AM3358-J adopt stwo AR8035 solution and there is no time out in both eths when ”ping ip -p 0xf0 -s 65000“

• the both eth1(AR8031/1000M) and eth0(AR8035/100M) of self-dev AM3358 board can be link up/down normally
• when I set eth1 at 1000M mode, ping with 65000 byte data length(pattern 0X00) is OK
• when I set eth1 at 1000M mode, ping with 65000 byte data length(pattern 0XF0)  the probability of time out is about(95%), then I find that when I ping with patern 0XF0 and the data length is >700 bytes, the ping test is most likely  failed
• when I set eth1 at 100M mode, it works good at any ping test conditions

• when I capture the TX_EN signal with oscilloscope, I find that both TMDSSK3358 and self-dev board have a 250MHz signal in TX_EN line, fig1 shows TX_EN in self-dev board; fig2 shows TX_EN in TMDSSK3358  board (under ping ip -p 0xf0 -s 65000 condition)

fig 1

fig 2

• I'm curious why self-dev board ping with pattern 0XF0 data length>700 is alway failed and why there exists a 250MHz signal? Could you give me some advise?

    

Part Number:TMS320C6748

I am attempting to test memory protection on the C6748.  I have been following this thread (https://e2e.ti.com/support/processors/f/791/t/158135#pi317270=2) and the mpuTest example provided, and I am able to run a test on my LCDK dev board with the debugger.  However, it isn't working as expected.

When I first ran the MPU test, it did not work as expected (same output as below).  I looked at the registers and saw that there were overlapping ranges configured, so I made some modifications to define them differently in case that was an issue.  Right now I am only focusing my efforts on MPU1.  

Here's the MPU1 configuration I'm doing at the start, then you can see in the output below how I change the MPPA register during the test:

#define MPU1_REGION_START_ADDR		    (0x80000000)
#define MPU1_REGION_SIZE                (0x00010000)
#define MPU1_TEST_ADDR                  (MPU1_REGION_START_ADDR + 0x20)


    // Setup the range we will be working with
    MPU1->PROG_RANGE[0].MPSAR = MPU1_REGION_START_ADDR;
    MPU1->PROG_RANGE[0].MPEAR = MPU1_REGION_START_ADDR + 0x400 - 1;
    MPU1->PROG_RANGE[0].MPPA = 0x03FFFEFF;  // full access to start

    // Clear the other ranges
    MPU1->PROG_RANGE[1].MPSAR = MPU1_REGION_START_ADDR + 0x400;
    MPU1->PROG_RANGE[1].MPEAR = MPU1_REGION_START_ADDR + 0x800 - 1;
    MPU1->PROG_RANGE[1].MPPA = 0x03FFFEC0;  // no access

    MPU1->PROG_RANGE[2].MPSAR = MPU1_REGION_START_ADDR + 0x800;
    MPU1->PROG_RANGE[2].MPEAR = MPU1_REGION_START_ADDR + 0xc00 - 1;
    MPU1->PROG_RANGE[2].MPPA = 0x03FFFEC0;  // no access

    MPU1->PROG_RANGE[3].MPSAR = MPU1_REGION_START_ADDR + 0xc00;
    MPU1->PROG_RANGE[3].MPEAR = MPU1_REGION_START_ADDR + 0x1000 - 1;
    MPU1->PROG_RANGE[3].MPPA = 0x03FFFEC0;  // no access

    MPU1->PROG_RANGE[4].MPSAR = MPU1_REGION_START_ADDR + 0x1000;
    MPU1->PROG_RANGE[4].MPEAR = MPU1_REGION_START_ADDR + 0x1400 - 1;
    MPU1->PROG_RANGE[4].MPPA = 0x03FFFEC0;  // no access

    MPU1->PROG_RANGE[5].MPSAR = MPU1_REGION_START_ADDR + 0x1400;
    MPU1->PROG_RANGE[5].MPEAR = MPU1_REGION_START_ADDR + 0x1800 - 1;
    MPU1->PROG_RANGE[5].MPPA = 0x03FFFEC0;  // no access

Here is the output I get, which clearly shows that no protection is occurring:

[C674X_0] MPU1 Testing Begins
------------------------------------------------------------------
FULL ACCESS: Memory protection set to = 0x03FFFEFF
FULL ACCESS: Value wrote to memory = 0x0BADBEEF
FULL ACCESS: Value read from memory = 0x0BADBEEF
NO ACCESS: Memory protection set to = 0x03FFFEC0
NO ACCESS: Value wrote to memory = 0x76543210
NO ACCESS: Value read from memory = 0x76543210
READ-ONLY ACCESS: Memory protection set to = 0x03FFFEE4
READ-ONLY ACCESS: Value wrote to memory = 0x01234567
READ-ONLY ACCESS: Value read from memory = 0x01234567
WRITE-ONLY ACCESS: Memory protection set to = 0x03FFFED2
WRITE-ONLY ACCESS: Value wrote to memory = 0xA5A50F0F
WRITE-ONLY ACCESS: Value read from memory = 0xA5A50F0F
READ/WRITE ACCESS: Memory protection set to = 0x03FFFEF6
READ/WRITE ACCESS: Value read from memory = 0xA5A50F0F
------------------------------------------------------------------

The register values also corroborate that what I'm writing to the registers looks correct (as far as I can tell):

0x01E14200  - 80000000 800003FF 03FFFEF6 00000000 80000400
0x01E14214  - 800007FF 03FFFEC0 00000000 80000800 80000BFF
0x01E14228  - 03FFFEC0 00000000 80000C00 80000FFF 03FFFEC0
0x01E1423C  - 00000000 80001000 800013FF 03FFFEC0 00000000
0x01E14250  - 80001400 800017FF 03FFFEC0 00000000 00000000

The value of 0x80000020 also matches up with the end of the test:

0x80000020  - A5A50F0F

Any suggestions as to what I might be doing wrong or what might be going on?  Is there something I'm missing about how the MPUs work?

Part Number:TMS320C6748

Question pertains to c6748 dsp.  How do you determine the cause of reset?  In particular, how do you differentiate between the reset due to POR vs watchdog reset?

Part Number:AM4378

Tool/software: Linux

environment

Linux host ubuntu 16.04

SDK 4.03.0.5

U-Boot 2017.01-00458-gccd1c34

custom board loosely based on the am4378 gp evm

we've had some issues getting the board to come up but we did finally get u-boot to start and run. now i am trying to get dhcp to happen and it isn't.

-------------------------------------------------------------------------------------------------------------------------------

our u-boot environment output is:

=> pr
arch=arm
args_mmc=run finduuid;setenv bootargs console=${console} ${optargs} root=PARTUU}
baudrate=115200
board=UTI-board
board_name=UTI-board
boot_fdt=try
boot_fit=0
bootcmd=run findfdt; run getuenv; setenv autoload no;dhcp ;tftp ${loadaddr} zIm}
bootdelay=2
bootdir=/boot
bootenvfile=uEnv.txt
bootfile=zImage-am437x-evm.bin
bootm_size=0x10000000
bootpart=0:2
bootscript=echo Running bootscript from mmc${mmcdev} ...; source ${loadaddr}
console=ttyO0,115200n8
cpu=armv7
devtype=mmc
dfu_alt_info_emmc=rawemmc raw 0 3751936;boot part 1 1;rootfs part 1 2;MLO fat 11
dfu_alt_info_mmc=boot part 0 1;rootfs part 0 2;MLO fat 0 1;MLO.raw raw 0x100 0x1
dfu_alt_info_qspi=u-boot.bin raw 0x0 0x080000;u-boot.backup raw 0x080000 0x08000
dfu_alt_info_ram=kernel ram 0x80200000 0x4000000;fdt ram 0x80f80000 0x80000;ram0
dfu_bufsiz=0x10000
envboot=mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device ${mm;
eth1addr=f0:b5:d1:3e:83:64
ethact=cpsw
ethaddr=f0:b5:d1:3e:83:62
fdt_addr_r=0x88000000
fdtaddr=0x88000000
fdtcontroladdr=9df111b8
fdtfile=am437x-UTI.dtb
finduuid=part uuid mmc ${bootpart} uuid
fit_bootfile=fitImage
fit_loadaddr=0x87000000
getuenv=setenv devnum ${mmcdev}; if mmc rescan; then if run loadbootenv; then r;
importbootenv=echo Importing environment from mmc${mmcdev} ...; env import -t $}
ip_method=dhcp
kernel_addr_r=0x82000000
loadaddr=0x82000000
loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}
loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr
loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}
loadfit=run args_mmc; bootm ${loadaddr}#${fdtfile};
loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}
loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz
mmcboot=mmc dev ${mmcdev}; setenv devnum ${mmcdev}; setenv devtype mmc; if mmc ;
mmcdev=0
mmcloados=run args_mmc; if test ${boot_fdt} = yes || test ${boot_fdt} = try; th;
mmcrootfstype=ext4 rootwait
mtdids=nand0=nand.0
mtdparts=mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.ba)
nandargs=setenv bootargs console=${console} ${optargs} root=${nandroot} rootfst}
nandboot=echo Booting from nand ...; run nandargs; nand read ${fdtaddr} NAND.u-}
nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096
nandrootfstype=ubifs rootwait=1
netargs=setenv bootargs console=${console} ${optargs} root=/dev/nfs nfsroot=${sp
netboot=echo Booting from network ...; setenv autoload no; dhcp; run netloadima}
netloadfdt=tftp ${fdtaddr} ${fdtfile}
netloadimage=tftp ${loadaddr} ${bootfile}
nfsopts=nolock,v3,tcp,rsize=4096,wsize=4096
partitions=uuid_disk=${uuid_gpt_disk};name=rootfs,start=2MiB,size=-,uuid=${uuid}
pxefile_addr_r=0x80100000
ramargs=setenv bootargs console=${console} ${optargs} root=${ramroot} rootfstyp}
ramdisk_addr_r=0x88080000
ramroot=/dev/ram0 rw
ramrootfstype=ext2
rdaddr=0x88080000
rootpath=/home/ULTRATEC/michael_j/ti-processor-sdk-linux-am437x-evm-04.03.00.05S
scriptaddr=0x80000000
serverip=192.168.61.105
soc=am33xx
static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off
stderr=serial@44e09000
stdin=serial@44e09000
stdout=serial@44e09000
update_to_fit=setenv loadaddr ${fit_loadaddr}; setenv bootfile ${fit_bootfile}
usbargs=setenv bootargs console=${console} ${optargs} root=${usbroot} rootfstyp}
usbboot=setenv devnum ${usbdev}; setenv devtype usb; usb start ${usbdev}; if usi
usbdev=0
usbroot=/dev/sda2 rw
usbrootfstype=ext4 rootwait
vendor=ti
ver=U-Boot 2017.01-00458-gccd1c34-dirty (Apr 03 2019 - 16:17:58 -0500)

Environment size: 5662/65532 bytes

-------------------------------------------------------------------------------------------------------------------------------

the pinmux for mii1 is:

static struct module_pin_mux mii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TCTL */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RCTL */
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TD3 */
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TD2 */
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TD1 */
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TD0 */
{OFFSET(mii1_txclk), MODE(0)}, /* MII1_TCLK */
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RCLK */
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RD3 */
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RD2 */
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RD1 */
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RD0 */
{OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
{OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{-1},
};

-------------------------------------------------------------------------------------------------------------------------------

the ethernet setup in the board.c looks like:

#ifndef CONFIG_DM_ETH
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* Additional controls can be added here */
return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 16,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 1,
},
};

static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
#endif

/*
* This function will:
* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
* in the environment
* Perform fixups to the PHY present on certain boards. We only need this
* function in:
* - SPL with either CPSW or USB ethernet support
* - Full U-Boot, with either CPSW or USB ethernet
* Build in only these cases to avoid warnings about unused variables
* when we build an SPL that has neither option but full U-Boot will.
*/
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \
defined(CONFIG_SPL_USBETH_SUPPORT)) && \
defined(CONFIG_SPL_BUILD)) || \
((defined(CONFIG_DRIVER_TI_CPSW) || \
defined(CONFIG_USB_ETHER)) && !defined(CONFIG_SPL_BUILD))
int board_eth_init(bd_t *bis)
{
int rv;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;

/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;

printf("Mac Addr = %x:%x:%x:%x:%x:%x\n", mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
if (!getenv("ethaddr")) {
puts("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}

#ifndef CONFIG_SPL_BUILD
mac_lo = readl(&cdev->macid1l);
mac_hi = readl(&cdev->macid1h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;

if (!getenv("eth1addr")) {
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("eth1addr", mac_addr);
}
#endif
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
cpsw_slaves[0].phy_addr = 1;

rv = cpsw_register(&cpsw_data);
if (rv < 0) {
printf("Error %d registering CPSW switch\n", rv);
return rv;
}
#endif

return rv;
}
#endif
#endif

-------------------------------------------------------------------------------------------------------------------------------

the output of the u-boot when trying to dhcp is:

U-Boot SPL 2017.01-00458-gccd1c34-dirty (Apr 03 2019 - 16:17:58)
Trying to boot from MMC1
SPL: Please implement spl_start_uboot() for your board
SPL: Direct Linux boot not active!
reading u-boot.img
reading u-boot.img
reading u-boot.img
reading u-boot.img

U-Boot 2017.01-00458-gccd1c34-dirty (Apr 03 2019 - 16:17:58 -0500)

CPU : AM437X-GP rev 1.2
Model: TI AM437x UTI BOARD
DRAM: 512 MiB
Pinmux for MII1_COL: 40000
Board Init
Power Init
PMIC: TPS65218
NAND: 0 MiB
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
reading uboot.env
Board late Init
Processes Called: 0
Net: Mac Addr = f0:b5:d1:3e:83:62
cpsw
Hit any key to stop autoboot: 0
## Error: "findfdt" not defined
reading uEnv.txt
717 bytes read in 4 ms (174.8 KiB/s)
Importing environment from mmc0 ...
link up on port 0, speed 100, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
BOOTP broadcast 6
BOOTP broadcast 7
BOOTP broadcast 8
BOOTP broadcast 9
BOOTP broadcast 10
BOOTP broadcast 11
BOOTP broadcast 12
BOOTP broadcast 13
BOOTP broadcast 14
BOOTP broadcast 15
BOOTP broadcast 16
BOOTP broadcast 17
BOOTP broadcast 18
BOOTP broadcast 19
BOOTP broadcast 20
BOOTP broadcast 21
BOOTP broadcast 22
BOOTP broadcast 23
BOOTP broadcast 24
BOOTP broadcast 25
BOOTP broadcast 26
BOOTP broadcast 27
BOOTP broadcast 28
BOOTP broadcast 29

Retry time exceeded; starting again
link up on port 0, speed 100, full duplex
*** ERROR: `ipaddr' not set
link up on port 0, speed 100, full duplex
*** ERROR: `ipaddr' not set

when i wireshark the line there are no DHCP packets present

the PHY reset is high so it is not in reset

where else do i look to fix this?

Part Number:AM3352

Tool/software: Linux

Hello!

Our product uses the MCSPI to send data to an FPGA, but after hundreds of thousands of successful SPI transactions, the SPI2 process freezes within an "uninterruptible sleep" (according to the ps command, the process is in a D state - uninterruptible sleep).  My Kernel Thread (custom network driver) then also locks up as it is waiting on the spi_async() call to return.   From web searches, I believe that the only code that can place the SPI2 process in this state is the "wait_for_completion" calls in the Tx & Rx DMA handlers.  

We are running Kernel 3.12 (but have manually updated to the MCSPI code from 3.14 due to the 64-byte SPI problem).  

This issue sounds very similar to another (locked) thread:  http://e2e.ti.com/support/processors/f/791/t/420294

Our MCSPI has the code changes mentioned in the first post of that thread, but the thread ends without listing a resolution.

We have also tried Kernel 4.9 with a similar lockup condition (not uninterruptible, but still locked up).

We are running the SPI at 8MHz using 16-bit word transactions,  DMA is used for data packet transfers.

Part Number:TMS320C6748

Hello,

I am trying to write data taken from an adc. I am at the point where i think i have mot of the registers on the mmcsd controller correctly but i need to send commands to the actual sd card to find its relative address and its voltage range. The technical reference guide tells me to send CMD0 but im not sure what value in the mmccmd register to send that command. Guides i have found for other boards have suggested values but this one does not. Does anyone have any experience using this controller?

Any help is appreciated,

Brian Dougenik

Part Number:DM3730

Tool/software: Code Composer Studio

Hello,

I'm attempting to connect to the ARM on my LogicPD DM3730 Torpedo board with CCS v5.5, and am getting an error (see console output below).

I'm using the Blackhawk XDS100v2 to connect to the board. I followed instructions in document: 1021646B_AN529_DM3730-AM3703_SOM_Creating_HelloWorld_Sample_App.pdf

to create the helloworld project for the AM3703 SOM. So I added GEL file and linker command file to the project as instructed. The connection test completes successfully.

When I launch the AM3703.ccxml target configuration and attempt to connect to the ARM, I get the console output below. Any idea why I get this error? I could not find anything/any solutions related to that error. Thank you.

-----------------

Cortex_A8_0: GEL Output: OMAP 32K Watchdog Timer is disable
Cortex_A8_0: GEL Output:  Putting DPLL into bypass before proceeding
Cortex_A8_0: GEL Output:  Putting CORE DPLL into bypass before proceeding
Cortex_A8_0: GEL Output:  Locking CORE DPLL
Cortex_A8_0: GEL Output:  PRCM clock configuration IIA setup has been completed
Cortex_A8_0: GEL Output:  SystemClock = 26.0 MHz
Cortex_A8_0: GEL Output:  DPLL_MULT_VALUE = 332
Cortex_A8_0: GEL Output:  DPLL_DIV_VALUE = 25
Cortex_A8_0: GEL Output:  CORE_DPLL_CLK = 664.0 MHz
Cortex_A8_0: GEL Output:  CORE_CLK = 332.0 MHz
Cortex_A8_0: GEL Output:  L3_CLK = 166.0 MHz
Cortex_A8_0: GEL Output: mDDR Hynix H8KDS0UN0MER - 2048 Mbit(256MB) on CS0, 16M x 32bit x 4Banks
Cortex_A8_0: Trouble Writing Memory Block at 0x6d000010 on Page 0 of Length 0x4: (Error -2130 @ 0x6D000010) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.1.232.0)
Cortex_A8_0: GEL: Error while executing OnTargetConnect(): Target failed to write 0x6D000010     at (*(SDRC_SYSCONFIG_REG)|=0x2) [am_dm37x_sdrc_configs.gel:403]     at SDRC_Reset() [am_dm37x_sdrc_configs.gel:337]     at mDDR_Hynix_H8KDS0UN0MER() [am_dm37x_cortexA.gel:221]     at OnTargetConnect() .
Cortex_A8_0: Trouble Reading Register CP15_Registers_CP15_CONTROL_REGISTER: (Error -2131 @ 0x20013F00) Unable to access device register. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.1.232.0)

Part Number:AM5749

Tool/software: Linux

According to 

I was doing this step ./oe-layertool-setup.sh -f configs/processor-sdk/processor-sdk-05.02.00.10-config.txt

But it gives me:

cloning repo bitbake

Fetching origin
Previous HEAD position was 0c7cf572... bitbake-user-manual: Added "usehead" parameter.
Switched to branch '1.36'
Your branch is up-to-date with 'origin/1.36'.
Already up-to-date.
Note: checking out '0c7cf572b8350e7ec1e451d207d67f1f7ce018cb'.

You are in 'detached HEAD' state. You can look around, make experimental
changes and commit them, and you can discard any commits you make in this
state without impacting any branches by performing another checkout.

If you want to create a new branch to retain commits you create, you may
do so (now or later) by using -b with the checkout command again. Example:

git checkout -b <new-branch-name>

HEAD is now at 0c7cf572... bitbake-user-manual: Added "usehead" parameter.

cloning repo meta-processor-sdk

Fetching origin
Previous HEAD position was 3788231... mmcsd-lld-rtos: SRCREV update to 01.00.00.14B
Switched to branch 'master'
Your branch is up-to-date with 'origin/master'.
Already up-to-date.
Note: checking out '378823175fb71bc7073ff4b745d62ee5b37de7bf'.

You are in 'detached HEAD' state. You can look around, make experimental
changes and commit them, and you can discard any commits you make in this
state without impacting any branches by performing another checkout.

If you want to create a new branch to retain commits you create, you may
do so (now or later) by using -b with the checkout command again. Example:

git checkout -b <new-branch-name>

HEAD is now at 3788231... mmcsd-lld-rtos: SRCREV update to 01.00.00.14B

cloning repo meta-ros

Cloning into '/home/will/tisdk/sources/meta-ros'...
fatal: unable to access 'github.com/.../': error setting certificate verify locations:
CAfile: /tmp/xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx/yyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyy/sy
ERROR: Could not clone repository at github.com/.../meta-ros.git

Do I need some certificate to download it ?

Part Number:TDA2P-ABZ

Tool/software: WEBENCH® Design Tools

Hello,

could you please help to look at the models of simulators used in TDA series?

Part Number:66AK2H12

We are using 66AK to develop a control platform.  Linux runs in the ARM cores. The control tasks are running in the DSP cores. We use  SGMII to communicate with other devices both in ARM and DSPcores.The first three SGMII channels are used by ARM ,and the last one is used by DSP core.So we have to use two separate queues to send SGMII datas, one for ARM and the other for DSP.   It appears queue number 648 must be used for GbE switch packet transmit,but we need send SGMII datas both in ARM and DSP simultaneously. See the  quesion replied on  the e2e forum.  https://e2e.ti.com/support/processors/f/791/t/784786       Whether 66AK meets our needs?  ARM config the first three SGMII serdes,QMSS and PKTDMA,it can work properly until DSP core configs the QMSS and PKTDMA again. Once DSP core reconfig QMSS and PKTDMA, the SGMII work abnormal.

How can we config the QMSS and PKTDMA which may be used both by ARM and DSP?  Can you provide an example?

Part Number:AM3359

Tool/software: Linux

Hello,

Please clarify the following doubts regarding GPMC communication with an external FPGA.

16 bit GPMC asynchronous mode is interfaced with FPGA using CS3 for normal data transfer & CS5 for DMA operation

1) If am transmitting 256kbytes over CS5 and at the same time I am operating CS3 for single write/read. How would be the behavior of GPMC. whether it will stop the DMA operation and start CS3 single write / read or immediately stop the DMA operation over CS5 ?

2) If am using 3 Chip selects. How would be the priority of data transfer operation over these chip selects ?

Waiting for your reply

thanks

Mobin P K

Tool/software: Linux

hello,

The platform chip that I use is am5728，I want to use the profinet industrial protocol. I see that it is not supported under linux SDK. So I want to know what is to be done under Linux system to implement the profinet procotol? where is the software solutions?

Part Number:PHYTC-3P-PHYCORE-AM335X

Tool/software: Linux

cpsw Waiting for PHY auto negotiation to complete......... TIMEOUT !
link up on port 0, speed 10, half duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
BOOTP broadcast 6
BOOTP broadcast 7
BOOTP broadcast 8
BOOTP broadcast 9
BOOTP broadcast 10

i have to set 10 mbps full duplex can any one have idea how to set ??

i am applying command mii write 1 0 <data> .

in <data> feild what should i put to get 10 mbps full duplex ??

Hi this DM3725 digital processor how much ram and memory support?

and its support memory interface ?

then how many GPIO ports are can accessible?

Part Number:DRA745

Tool/software: Linux

Hi,expert,

I want to automatically run app.out when the boot the system.

I add init=/home/root/init-demo.sh to uenv.txt.

change  LAUNCH_DEMO=1 in init-demo.sh.

But I got an error .the log as below:

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Initializing cgroup subsys cpuacct
[    0.000000] Linux version 4.4.84-00029-g1b6c2992-dirty (adas@ps-15b-devik) (gcc version 5.3.1 20160113 (Linaro GCC 5.3-2016.02) ) #24 SMP PREEMPT Wed Mar 20 16:17:13 CST 2019
[    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] Machine model: TI DRA742
[    0.000000] Reserved memory: created DMA memory pool at 0x40300000, size 3 MiB
[    0.000000] Reserved memory: initialized node cmem@40300000, compatible id shared-dma-pool
[    0.000000] Reserved memory: regions without no-map are not yet supported
[    0.000000] Reserved memory: created CMA memory pool at 0x99000000, size 32 MiB
[    0.000000] Reserved memory: initialized node ipu2_cma@88000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x9b000000, size 16 MiB
[    0.000000] Reserved memory: initialized node dsp1_cma@8A000800, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x9c000000, size 16 MiB
[    0.000000] Reserved memory: initialized node dsp2_cma@8A001000, compatible id shared-dma-pool
[    0.000000] Reserved memory: incorrect alignment of CMA region
[    0.000000] Reserved memory: regions without no-map are not yet supported
[    0.000000] Reserved memory: created DMA memory pool at 0x9d200000, size 32 MiB
[    0.000000] Reserved memory: initialized node cmem@9D200000, compatible id shared-dma-pool
[    0.000000] Reserved memory: regions without no-map are not yet supported
[    0.000000] cma: Reserved 24 MiB at 0x97800000
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] OMAP4: Map 0x9fe00000 to fe600000 for dram barrier
[    0.000000] On node 0 totalpages: 122368
[    0.000000] free_area_init_node: node 0, pgdat c08e7340, node_mem_map df64c000
[    0.000000]   Normal zone: 1152 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 122368 pages, LIFO batch:31
[    0.000000] DRA752 ES1.1
[    0.000000] PERCPU: Embedded 11 pages/cpu @df5d3000 s14912 r8192 d21952 u45056
[    0.000000] pcpu-alloc: s14912 r8192 d21952 u45056 alloc=11*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1 
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 121216
[    0.000000] Kernel command line: console=ttyO0,115200n8 vram=16M root=PARTUUID=2366589b-02 rw rootwait ip=none mem=512M loglevel=8 init=/home/root/init-demo.sh
[    0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Memory: 64012K/489472K available (6087K kernel code, 318K rwdata, 2356K rodata, 328K init, 286K bss, 335348K reserved, 90112K cma-reserved, 0K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xe0800000 - 0xff800000   ( 496 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc084701c   (8445 kB)
[    0.000000]       .init : 0xc0848000 - 0xc089a000   ( 328 kB)
[    0.000000]       .data : 0xc089a000 - 0xc08e9970   ( 319 kB)
[    0.000000]        .bss : 0xc08eb000 - 0xc0932990   ( 287 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  Build-time adjustment of leaf fanout to 32.
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] ti_dt_clocks_register: failed to lookup clock node gmac_gmii_ref_clk_div
[    0.000000] OMAP clockevent source: timer1 at 32786 Hz
[    0.000000] Architected cp15 timer(s) running at 6.14MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[    0.000004] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
[    0.000016] Switching to timer-based delay loop, resolution 162ns
[    0.000418] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000426] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000956] Console: colour dummy device 80x30
[    0.000976] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
[    0.000982] This ensures that you still see kernel messages. Please
[    0.000988] update your kernel commandline.
[    0.001000] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
[    0.001013] pid_max: default: 32768 minimum: 301
[    0.001109] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.001119] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.001747] Initializing cgroup subsys io
[    0.001765] Initializing cgroup subsys memory
[    0.001792] Initializing cgroup subsys devices
[    0.001805] Initializing cgroup subsys freezer
[    0.001817] Initializing cgroup subsys perf_event
[    0.001830] Initializing cgroup subsys pids
[    0.001858] CPU: Testing write buffer coherency: ok
[    0.002084] /cpus/cpu@0 missing clock-frequency property
[    0.002100] /cpus/cpu@1 missing clock-frequency property
[    0.002111] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.002155] Setting up static identity map for 0x80008340 - 0x800083a0
[    0.080018] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.080083] Brought up 2 CPUs
[    0.080097] SMP: Total of 2 processors activated (24.59 BogoMIPS).
[    0.080104] CPU: All CPU(s) started in HYP mode.
[    0.080110] CPU: Virtualization extensions available.
[    0.081195] devtmpfs: initialized
[    0.111514] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[    0.112466] omap_hwmod: l3_main_2 using broken dt data from ocp
[    0.316080] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.316104] futex hash table entries: 512 (order: 3, 32768 bytes)
[    0.318262] pinctrl core: initialized pinctrl subsystem
[    0.319151] NET: Registered protocol family 16
[    0.320125] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.350218] cpuidle: using governor ladder
[    0.380242] cpuidle: using governor menu
[    0.389121] OMAP GPIO hardware version 0.1
[    0.395916] irq: no irq domain found for /ocp/l4@4a000000/scm@2000/pinmux@1400 !
[    0.411993] omap-gpmc 50000000.gpmc: GPMC revision 6.0
[    0.412006] gpmc_mem_init: disabling cs 0 mapped at 0x0-0x1000000
[    0.420966] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[    0.420976] hw-breakpoint: maximum watchpoint size is 8 bytes.
[    0.421498] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[    0.421507] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[    0.422026] OMAP DMA hardware revision 0.0
[    0.462159] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[    0.463382] edma 43300000.edma: memcpy is disabled
[    0.468353] edma 43300000.edma: TI EDMA DMA engine driver
[    0.472406] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[    0.472601] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[    0.472768] omap-iommu 58882000.mmu: 58882000.mmu registered
[    0.472926] omap-iommu 55082000.mmu: 55082000.mmu registered
[    0.473221] omap-iommu 41501000.mmu: 41501000.mmu registered
[    0.473424] omap-iommu 41502000.mmu: 41502000.mmu registered
[    0.476855] palmas 0-0058: IRQ missing: skipping irq request
[    0.490777] palmas 0-0058: Muxing GPIO 2e, PWM 0, LED 0
[    0.562763] pcf857x: probe of 0-0021 failed with error -121
[    0.562808] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
[    0.563225] omap_i2c 48060000.i2c: bus 2 rev0.12 at 400 kHz
[    0.563438] media: Linux media interface: v0.10
[    0.563491] Linux video capture interface: v2.00
[    0.563534] pps_core: LinuxPPS API ver. 1 registered
[    0.563541] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.563568] PTP clock support registered
[    0.563621] EDAC MC: Ver: 3.0.0
[    0.564404] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[    0.564700] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
[    0.565056] Advanced Linux Sound Architecture Driver Initialized.
[    0.565948] clocksource: Switched to clocksource arch_sys_counter
[    0.577010] NET: Registered protocol family 2
[    0.577560] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
[    0.577600] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
[    0.577667] TCP: Hash tables configured (established 4096 bind 4096)
[    0.577709] UDP hash table entries: 256 (order: 1, 8192 bytes)
[    0.577729] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[    0.577933] NET: Registered protocol family 1
[    0.578190] RPC: Registered named UNIX socket transport module.
[    0.578198] RPC: Registered udp transport module.
[    0.578205] RPC: Registered tcp transport module.
[    0.578212] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.578231] PCI: CLS 0 bytes, default 64
[    0.579330] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
[    0.588620] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.589259] NFS: Registering the id_resolver key type
[    0.589288] Key type id_resolver registered
[    0.589296] Key type id_legacy registered
[    0.589360] ntfs: driver 2.1.32 [Flags: R/O].
[    0.590800] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[    0.590817] io scheduler noop registered
[    0.590830] io scheduler deadline registered
[    0.590864] io scheduler cfq registered (default)
[    0.596149] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[    0.599595] PCI host bridge /ocp/axi@0/pcie_rc@51000000 ranges:
[    0.599608]   No bus range found for /ocp/axi@0/pcie_rc@51000000, using [bus 00-ff]
[    0.599640]    IO 0x20003000..0x20012fff -> 0x00000000
[    0.599662]   MEM 0x20013000..0x2fffffff -> 0x20013000
[    0.631909] dra7-pcie 51000000.pcie_rc: link is not up
[    0.632077] dra7-pcie 51000000.pcie_rc: PCI host bridge to bus 0000:00
[    0.632089] pci_bus 0000:00: root bus resource [bus 00-ff]
[    0.632101] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    0.632111] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[    0.632145] pci 0000:00:00.0: [104c:8888] type 01 class 0x060400
[    0.632189] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
[    0.632211] pci 0000:00:00.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[    0.632281] pci 0000:00:00.0: supports D1
[    0.632290] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[    0.632523] PCI: bus0: Fast back to back transfers disabled
[    0.632644] PCI: bus1: Fast back to back transfers enabled
[    0.632727] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff]
[    0.632742] pci 0000:00:00.0: BAR 1: assigned [mem 0x20020000-0x2002ffff]
[    0.632755] pci 0000:00:00.0: PCI bridge to [bus 01]
[    0.632992] pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt
[    0.633005] pcie_pme 0000:00:00.0:pcie01: service driver pcie_pme loaded
[    0.633135] aer 0000:00:00.0:pcie02: service driver aer loaded
[    0.697281] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[    0.700702] 4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 301, base_baud = 3000000) is a 8250
[    1.766914] console [ttyS0] enabled
[    1.771308] 4806c000.serial: ttyS1 at MMIO 0x4806c000 (irq = 302, base_baud = 3000000) is a 8250
[    1.781020] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 303, base_baud = 3000000) is a 8250
[    1.791352] [drm] Initialized drm 1.1.0 20060810
[    1.796958] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    1.803601] [drm] No driver support for vblank timestamp query.
[    1.809778] [drm] Initialized vdrm 1.0.0 20110917 on minor 0
[    1.817130] OMAP DSS rev 6.1
[    1.820897] omapdss_dss 58000000.dss: bound 58001000.dispc (ops dispc_component_ops)
[    1.836976] loop: module loaded
[    1.840498] vmemexp device MAJOR num = 245
[    1.844625] vmemexp class registered
[    1.848362] /dev/vmemexp device registered
[    1.852475] ioctl DBUFIOC_EXPORT_VIRTMEM = -1072899120
[    1.861533] libphy: Fixed MDIO Bus: probed
[    1.915982] davinci_mdio 48485000.mdio: davinci mdio revision 1.6
[    1.922104] davinci_mdio 48485000.mdio: no live phy, scanning all
[    1.929719] davinci_mdio: probe of 48485000.mdio failed with error -5
[    1.936864] cpsw 48484000.ethernet: Detected MACID = 34:03:de:e5:96:48
[    1.943521] cpsw 48484000.ethernet: cpts: overflow check period 800
[    1.950533] cpsw 48484000.ethernet: cpsw: Detected MACID = 34:03:de:e5:96:49
[    1.959261] mousedev: PS/2 mouse device common for all mice
[    1.965537] i2c /dev entries driver
[    1.974637] omap_hsmmc 4809c000.mmc: Got CD GPIO
[    2.026833] ledtrig-cpu: registered to indicate activity on CPUs
[    2.047816] davinci-mcasp 48468000.mcasp: ERRATA i868 workaround is enabled
[    2.055015] davinci-mcasp 4847c000.mcasp: invalid tdm slots: 0
[    2.077543] NET: Registered protocol family 10
[    2.086515] sit: IPv6 over IPv4 tunneling driver
[    2.091735] NET: Registered protocol family 17
[    2.096451] Key type dns_resolver registered
[    2.100889] omap_voltage_late_init: Voltage driver support not added
[    2.107799] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.oppdm
[    2.114007] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.oppdm
[    2.120721] Adding alias for supply vdd,cpu0 -> vdd,4a003b20.oppdm
[    2.126953] Adding alias for supply vbb,cpu0 -> vbb,4a003b20.oppdm
[    2.134293] Power Management for TI OMAP4+ devices.
[    2.139423] Registering SWP/SWPB emulation handler
[    2.145603] dmm 4e000000.dmm: workaround for errata i878 in use
[    2.153318] dmm 4e000000.dmm: initialized all PAT entries
[    2.161272] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    2.167938] [drm] No driver support for vblank timestamp query.
[    2.174372] [drm] Initialized omapdrm 1.0.0 20110917 on minor 1
[    2.181846] hctosys: unable to open rtc device (rtc0)
[    2.193213] mmc0: host does not support reading read-only switch, assuming write-enable
[    2.201391] evm_1v8: disabling
[    2.203267] mmc0: new high speed SDHC card at address 59b4
[    2.210014] vmmcwl_fixed: disabling
[    2.213723] ldousb: disabling
[    2.213850] mmcblk0: mmc0:59b4 USD   7.51 GiB 
[    2.217482]  mmcblk0: p1 p2
[    2.224520] ALSA device list:
[    2.227519]   No soundcards found.
[    2.232550] EXT4-fs (mmcblk0p2): couldn't mount as ext3 due to feature incompatibilities
[    2.241237] EXT4-fs (mmcblk0p2): couldn't mount as ext2 due to feature incompatibilities
[    2.274320] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[    2.282528] VFS: Mounted root (ext4 filesystem) on device 179:2.
[    2.289374] devtmpfs: mounted
[    2.292629] Freeing unused kernel memory: 328K
[    2.297109] This architecture does not have kernel memory protection.
mount: unknown filesystem type 'dev'
dra7-ipu2-fw.xem4 loaded already
[    2.929024] [drm] Initialized pvr 1.14.3699939 20110701 on minor 2
[    3.017318] PVR_K: UM DDK-(3699939) and KM DDK-(3699939) match. [ OK ]
Loaded PowerVR consumer services.
[    3.102326] DMA: Module install successful, device major num = 242 
[    3.108730] DRV: Module install successful
insmod: ERROR: could not load module ./bin/cmemk.ko: No such file or directory
./disableDssInterruptsOnA15.sh: line 11: @0x4A002ACA:: command not found
./disableDssInterruptsOnA15.sh: line 12: @0x4A002ACA:: command not found
./disableDssInterruptsOnA15.sh: line 13: @0x4A002ACA:: command not found
./disableDssInterruptsOnA15.sh: line 14: @0x4A002ACA:: command not found
./disableDssInterruptsOnA15.sh: line 15: @0x4A002ACA:: command not found
./disableDssInterruptsOnA15.sh: line 16: @0x4A002ACA:: command not found
./disableDssInterruptsOnA15.sh: line 17: @0x4A002ACA:: command not found
./disableDssInterruptsOnA15.sh: line 18: @0x4A002ACA:: command not found
./disableDssInterruptsOnA15.sh: line 19: @0x4A002ACA:: command not found
updated 0x4A002ACA value is 00930000
 [HOST]  OSA: MEM: 0: Mapped 0x9fc00000 to 0xb69ea000 of size 0x00100000 
 [HOST]  OSA: MEM: 1: Mapped 0x84203000 to 0xa6cea000 of size 0x0fd00000 
 [HOST]  OSA: MEM: 2: Mapped 0x9fd00000 to 0xa6c2a000 of size 0x00040000 
 [HOST]  OSA: MEM: 3: Mapped 0x9fdc0000 to 0xa6c6a000 of size 0x00080000 
 [HOST]  OSA: MEM: 4: Mapped 0x00000000 to 0x00000000 of size 0x00000000 
 [HOST]  OSA: HOST Remote Log Shared Memory @ 0x9fd4f140
 [HOST]  OSA: IPU2 Remote Log Shared Memory @ 0x9fe63da0
 [HOST] [HOST  ]      9.275910 s:  SYSTEM: System A15 Init in progress !!!

Please give some suggestions.

Part Number:AM4372

Hi Sitara Support Team,

I would like to just make sure the followings item,
can GPMC CS0-CS3 of AM437x set 8 bit or 16 bit individually in each CS block?

It will use NOR flash device on the custom' s system.

Best regards,
Kanae

Part Number:PROCESSOR-SDK-AM335X

Tool/software: Linux

Kernel version 4.4.32-gadde2ca9f8
Arago based filesytem

i have to boot from nfs 
i used this commands 
-------------------------------------------------------------------
setenv netboot 'echo Booting from network ...; setenv autoload no; run netloadimage; run netloadfdt; run netargs; bootz ${loadaddr} - ${fdtaddr}';
setenv netargs 'setenv bootargs console=${console} ${optargs} root=/dev/nfs nfsroot=<SERVERIP>:${rootpath},${nfsopts} rw ip=dhcp';
setenv bootfile zImage; setenv fdtfile am335x-prcheck.dtb;
setenv serverip <SERVERIP>;
setenv rootpath <FileSystem>;
run netboot
-------------------------------------------------------------------

to enter these commands i have to get IP of the device through "dhcp" command and it shows


-------------------------------------------------------------------
U-Boot 2016.05-g9c1d5f2-dirty (Nov 09 2018 - 16:17:20 -0500)

CPU : AM335X-GP rev 2.1
Model: TI AM335x EVM
Watchdog enabled
DRAM: 512 MiB
NAND: 512 MiB
MMC: initializing MMC : 0
probing MMCs
Probing MMC 2
return from mmc device -19
OMAP SD/MMC: 0, OMAP SD/MMC: 1
Doing preinit
Card did not respond to voltage select!
** Bad device mmc 0 **
Using default environment

<ethaddr> not set. Validating first E-fuse MAC
Net: RMII mode configure for PHY 1
cpsw, usb_ether
Press SPACE to abort autoboot in 2 seconds
PRCHECK# dhcp
cpsw Waiting for PHY auto negotiation to complete.. done
link up on port 0, speed 100, full duplex
link up on port 0, speed 100, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
BOOTP broadcast 6
BOOTP broadcast 7
BOOTP broadcast 8
BOOTP broadcast 9
BOOTP broadcast 10
BOOTP broadcast 11
BOOTP broadcast 12
BOOTP broadcast 13
BOOTP broadcast 14
BOOTP broadcast 15
BOOTP broadcast 16
BOOTP broadcast 17
BOOTP broadcast 18
BOOTP broadcast 19
BOOTP broadcast 20
BOOTP broadcast 21
BOOTP broadcast 22
BOOTP broadcast 23
BOOTP broadcast 24
BOOTP broadcast 25
BOOTP broadcast 26
BOOTP broadcast 27
BOOTP broadcast 28
BOOTP broadcast 29

Retry time exceeded; starting again
-------------------------------------------------------------------
PRCHECK# mii info
PHY 0x01: OUI = 0x80017, Model = 0x09, Rev = 0x00, 10baseT, HDX
-------------------------------------------------------------------
PRCHECK# mii dump 1 0
0. (3100) -- PHY control register --
(8000:0000) 0.15 = 0 reset
(4000:0000) 0.14 = 0 loopback
(2040:2000) 0. 6,13 = b01 speed selection = 100 Mbps
(1000:1000) 0.12 = 1 A/N enable
(0800:0000) 0.11 = 0 power-down
(0400:0000) 0.10 = 0 isolate
(0200:0000) 0. 9 = 0 restart A/N
(0100:0100) 0. 8 = 1 duplex = full
(0080:0000) 0. 7 = 0 collision test enable
(003f:0000) 0. 5- 0 = 0 (reserved)
-------------------------------------------------------------------

I have to set it 10 mbps with full duplex

Part Number:OMAP-L138

Tool/software: Linux

1、What does each line of screen printing on the chip surface mean? Is the red line marked for batch information?

2.At present, our company's production line feedback has the following failure phenomena, whether it is related to chip anomalies?

1)Program can not be downloaded, JTAG can not be connected, test power supply voltage is normal, FLASH no load signal

2)The download program is successful, you can't read back version information, test with JTAG, the connection is not smooth, you can't configure DDRAM, test the power supply voltage is normal.

3)Download the program successfully, can not read back version information, test with JTAG, the program loaded into DDRAM and run away

4)The download program is successful, the version information can be read back, and the program runs normally.