Can PCIe Gen3 root complex support Gen4 PCIe Bridge switch device.

Part Number:TDA3XEVM

Tool/software: Linux

Hi,

Please help me to find guidelines to setup Yocto configuration files or Yocto set up for vision SDK for TDA3MA.

Is SDK_VISION_03_06_00_00 is latest SDK for this platform

Thanks and Regards

Vishal Singh

Part Number:TMS320C6678

Hi,

I have been going through the CorePac 66x user guide and the TMS320C6678 manual. But I haven't been able to figure out how to setup an exception when the software accesses a NULL-pointer (address 0x0)

The Corepac C66x user guide XMC description Figure 7-10 list the lower part of the memory as "Non-remappable" which hints at the lower part of the addressing space does not go though the XMC port. Thus the XMC registers cannot be used.

In the TMS320C6678 manual "2.3 Memory Map Summary"

0x0-0x7FFFFF is listed as "Reserved" with L2 SRAM starting at 0x800000.

So which module protects accesses to this area? Which exception will be generated?

Part Number:TDA2P-ACD

Tool/software: TI-RTOS

Hi,

I want to change frame rate of HDMI output from 1080p@60fps to 1080p@30fps. What should I modify in order to achieve that? I am using PROCESSOR_SDK_VISION_03_05_00_00.

Regards,

Suzana

Part Number:AM3352

Tool/software: Linux

Hi,

I am using custom board with AM3352 processor, which is connected with STM32 controller on SPI interface. In our case, STM controller is the master of this SPI connection and AM3352 is the slave. We have developed our custom driver for AM3352 to work in slave mode and communicate with the master.

Using this driver, the slave is able to send the data to master but at the time of receiving the data from the master, the driver is not generating interrupt. I found using "omapconf" application that data is received in SPI RX0 buffer. But somehow the interrupt is not generated.

Following are the configuration of SPI registers at the time of receiving the data:

MCSPI_CH0CONF: 10061380

MCSPI_IRQENABLE: 00000004

MCSPI_MODULCTRL: 00000006

In our case SPID0 is MISO (output for AM3352) and SPID1 is MOSI(Input for AM3352). We are using gpio for chip select and able to get interrupt for it. Following are the registered interrupts where SPI_SLAVE_CS is chip select interrupt and SPI_SLAVE_RCVR is SPI interrupt.

root@myboard:~# cat /proc/interrupts
           CPU0       
 16:      41802      INTC  68 Level     gp_timer
 20:       3577      INTC  12 Level     49000000.edma_ccint
 22:         45      INTC  14 Level     49000000.edma_ccerrint
 26:          3      INTC  96 Level     44e07000.gpio
 46:          2  44e07000.gpio  19 Edge      wl18xx
 56:          1  44e07000.gpio  29 Edge      eth0
 59:          0      INTC  98 Level     4804c000.gpio
 65:          0  4804c000.gpio   5 Edge      SPI_SLAVE_RCVR
 92:        444      INTC  32 Level     481ac000.gpio
114:        444  481ac000.gpio  21 Edge      SPI_SLAVE_CS
125:          0      INTC  62 Level     481ae000.gpio
158:       3651      INTC  72 Level     OMAP UART0
159:         12      INTC  74 Level   
161:        276      INTC  70 Level     44e0b000.i2c
162:          3      INTC  71 Level     4802a000.i2c
163:         60      INTC  30 Level     4819c000.i2c
164:       8512      INTC  64 Level     mmc1
165:        621      INTC  28 Level     mmc2
166:       1412      INTC  29 Level     mmc0
180:          0      INTC 111 Level     48310000.rng
181:         51      INTC  18 Level     musb-hdrc.0
182:          0      INTC  17 Level     47400000.dma-controller
Err:          0
root@myboard:~#

Am I missing any configuration to generate interrupt on data receiving in Rx0 buffer?

Regards,

Rohit

Part Number:PROCESSOR-SDK-AM57X

Tool/software: TI-RTOS

I want to build the IPC example demos but failed. just as the picture below:

I do not know how to install Processor SDK RTOS 05.01.00.11 for am57xx-evm, I think I have installed it already(since the directory is /~/ti/ti-processor-sdk-linux-rt-am57xx-evm-05.01.00.11$);

And I also do not know what is the TI_RTOS_PATH is. could you please tell me?

thanks.

Part Number:TDA2

To add the 5^thAWR1243 here are the pinout changes we are planning to the cascade radar reference design. Can you confirm we are not using any pins incorrectly?

With Muxmode = 7

Pins needed for 5^thAWR1243:

Pin          remove                                                                                add

C14      open                                                                                 vin6a_fld0                          

G12        I2C5_SDA                                                                           vin6a_vsyn 

F12        I2C5_SCL                                                                              vin6a_hsyn

B13         TDA_FPGA_SPI_SEL_A_GPIO5_12                             VIN6A_D13

A12        TDA_FPGA_SPI_SEL_B_GPIO4_17                             VIN6A_D12                                

E14         TDA_AWR1_GPIO0_GPIO4_18                                   VIN6A_D11

A13        TDA_AWR1_GPIO1_GPIO6_4                                     VIN6A_D10

G14        TDA_AWR1_GPIO2_GPIO6_5                                     VIN6A_D9

F14       open                                                                                      VIN6A_D8

B12        TDA_AWR2_SPI_INT_GPIO5_10                                VIN6A_D15

A11        TDA_AWR3_SPI_INT_GPIO5_11                                VIN6A_D14

D14        open                                                                                     VIN6A_DE0

A19        open                                                                                     VIN6A_D7

C15         open                                                                                     VIN6A_D5

A16        open                                                                                     VIN6A_D4

A18        open                                                                                     VIN6A_D6

B18         open                                                                                     VIN6A_D3

B19        open                                                                                     VIN6A_D1

C17        open                                                                                     VIN6A_D0

F15         open                                                                                     VIN6A_D2

E17         open                                                                                     VIN6A_CLK0

D18        open                                                                                     VIN6A_D0

Move these signals to new pins:

Pin          remove                                                                                add

AA3        TDA_VIN4A_D20                                                              I2C5_SDA               

AB9        TDA_VIN4A_D21                                                              I2C5_SCL

C18         TDA_VIN4A_D16                                                              TDA_AWR2_SPI_INT_GPIO5_10

A21        TDA_VIN4A_D17                                                              TDA_AWR3_SPI_INT_GPIO5_11

G16        TDA_VIN4A_D18                                                              TDA_AWR1_GPIO0_GPIO4_18

D17        TDA_VIN4A_D19                                                              TDA_AWR1_GPIO1_GPIO6_4

AB3        TDA_VIN4A_D22                                                              TDA_AWR1_GPIO2_GPIO6_5

R6           TDA_VIN3A_MUX_D16                                                 TDA_FPGA_SPI_SEL_A_GPIO5_12

T9           TDA_VIN3A_MUX_D17                                                 TDA_FPGA_SPI_SEL_B_GPIO4_17

Part Number:AM5749

Hi,

I'll use the PCIe subsystem controller as dual-lane port to interface a M.2 2242 SSD Flash.

I would like to know if the Gen2 PCIe controller support a Gen3 PCIe device, assuming the speed limitation.

Thank you,

Sylvain.

Part Number:PROCESSOR-SDK-AM57X

Tool/software: TI-RTOS

Hello,

I'm using AM572x IDK board with TI-RTOS SDK 05.01.00.11.

I want to implement that logic:

• Detect EMMC memory fatfs formatting status (formatted/not formatted)
• Format emmc, if required
• Work with formatted emmc: read/write files

I implement it with that code:

FATFS_Error err = FATFS_OK;
char open_path[] = "1:path.txt";
int emmc_fat_index = 1;
FRESULT fat_err;
FIL f;

EmmcsReset();
FATFS_init();

err = FATFS_open(emmc_fat_index, NULL, &FatfsInit_emmcHandle);
if (err != FATFS_OK) {
    Log_error1("ERROR: Cannot init emmc card. Error code %d\n", err);
    return;
}

// try to open file
fat_err = f_open(&f, open_path, FA_READ);
if (fat_err == FR_NO_FILESYSTEM) {
    Log_warning0("Cannot found emmc file system");

    /* Create FAT volume */
    res = f_mkfs(open_path, 0, 0);
    if (res != FR_OK){
       Log_error1("Cannot create emmc file system. Error code %d", res);
    } else {
        Log_info0("Emmc formatting completed");
    }
}
if (fat_err == FR_OK)
{
    // file not need
    f_close(&f);
}
if (fat_err == FR_OK || fat_err == FR_NO_FILE || fat_err == FR_NO_PATH)
{
    Log_info0("Filesystem on emmc was found");
}

But that code doesn't work as I want: f_mkfs() call returns error code 3. I debugged the library, and that error generates when fatfs driver call MMCSD_init() function again (first call was in f_open()).

I tried to close file system with FATFS_close(&FatfsInit_emmcHandle) function before f_mkfs() function call, but my code crashes (because ((FATFS_Config *) handle)->object has NULL value).

How should I implement the required logic?

With regards,
Alex

P.S. I rebuilt PDK fatfs driver with #define _USE_MKFS 1 option and rebuild project after that.
P.P.S. eMMC memory works, because eMMC PDK example test works fine.

Part Number:TDA2PXEVM

In PROCESSOR_SDK_VISION (ver 3.6), in chains_common_cascade_ar12xx_config_mimo.c, line 203 mentions "/*profileCfgArgs[1].numAdcSamples * 2 - 512 * 2*/". I believe 512 is the maximum possible value that can be entered for numAdcSamples for complex FFT calculations. As numAdcSamples is used to determine the Range FFT, this limits the maximum possible Range FFT using TDA2px. Could you tell me what is causing this limitation? Is it because of any particular Hardware component (for eg buffer size)? I tried entering 1024 to increase the FFT size, but then my frame rate reduced drastically. What might be causing this issue?

I look forward to your reply.

Best Regards,

Nishant

Part Number:TDA3

Hi,

Can somebody please explain me the significance of the following parameters:

1. In acfJAcintoExample.m

config.nNeg=20000;
config.nAccNeg=60000;
%opts.pPyramid.nApprox=-1; %TODO: just for speed. comment this out later.
config.pLoad=['hRng',[56 inf], 'wRng',[24 inf], pLoadLabel];

2. In acfJacintoTrainTest.m 

opts.modelDs=[56 24]; opts.modelDsPad=[64 64];

opts.nWeak=[32 128 512 2048];
opts.pJitter=struct('flip',1);
opts.pBoost.pTree.fracFtrs=1/16;
aRatio=opts.modelDs(2)/opts.modelDs(1);opts.pLoad={'squarify',{3,aRatio}};

%set eval range - optional
opts.pLoad = [opts.pLoad 'hRng',[opts.modelDs(1) inf], 'wRng',[opts.modelDs(2) inf]];
opts.name=['models/' exptName];
opts.pPyramid.pChns.pFastMode.enabled=1; %default: 0
show=2;

if opts.pPyramid.pChns.pFastMode.enabled,
opts.cascThr=-1; %default: -1
opts.detThr=0; %default: -1
opts.cascCal=0; %default: 0.005 or 0.01(below)
opts.detOffset=0; %position offset for detection. default: 0 is best for quality.

%opts.adjustPyramidPad=0; %pyramid padding adjustment in acfTrain(). Pyramid padding is better for accuracy.
%opts.pPyramid.pad=[0,0]; %default: ceil((opts.modelDsPad-opts.modelDs)/shrink/2)*shrink;
opts.pPyramid.nApprox=0; %default: -1 (fastest). This parameter affects the speed (and accuracy) a lot.
opts.pPyramid.smooth=0; %default: 1

opts.pPyramid.pChns.pColor.smooth=0; %default: 1, 0 seems much better in jacinto config
opts.pPyramid.pChns.pGradMag.normRad=0; %default: 5, 0 is okay
%opts.pPyramid.pChns.pGradMag.full=0; %default: 0, 0 is better than 1
%opts.pPyramid.pChns.pGradHist.softBin=-2; %default: 0(spatial soft bin), -2: no soft bin, other, trilinear soft bin (best quality: -1)
%opts.pPyramid.pChns.pGradHist.useHog=0; %already set

opts.nWeak=[32 128 512 1280 2048 2048]; %stages in training
opts.nNeg=10000; %num negatives to be collected in a stage
opts.nAccNeg=20000; %num accumulated negatives to be collected
opts.bsOlap=0.01; %default: 0.1, best: 0.01, booststrap overlap for hard negative selection
else
opts.cascCal=0.01; %default: 0.005 or 0.01(below)
end

%% optionally switch to LDCF version of detector (see acfTrain)

if( 0 )

opts.filters=[5 4]; opts.pJitter=struct('flip',1,'nTrn',3,'mTrn',1);
opts.pBoost.pTree.maxDepth=3; opts.pBoost.discrete=0; opts.seed=2;
opts.pPyramid.pChns.shrink=2; opts.name=['models/' exptName];
end

what are these variables (I read the comments but still c)? and how does their values impact the training?

I trained with CallTech USA dataset, and tested the OD code with the new descriptor file generated after this training but the results are very bad. I used jpg images with pedestrians from internet and converted them to YUV42-NV12 format and used Feature Plane generation app to generate .bin file which are used as input to test TI OD algorithm. 

As the results are not good, I want to know the significance of the above training parameters just to know if I could improve the accuracy?

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

I downloaded the Calltech Usa datasets and modified the paths for videos and vbbList as follows:

objectName='Person';
exptName='AcfJacintoClatechUsa';
extractType='annotated';
extractFormat='jpg'; %png; %'';
dataDir='E:\HOG_SVM\Training_datasets_SVM\Calltech_for_Adaboost';
vidList={ ...
{'videos/set00/V000.seq', 'videos/set00/V001.seq','videos/set00/V002.seq', 'videos/set00/V003.seq','videos/set00/V004.seq', 'videos/set00/V005.seq', ...
'videos/set00/V006.seq', 'videos/set00/V007.seq','videos/set00/V008.seq', 'videos/set00/V009.seq','videos/set00/V010.seq', 'videos/set00/V011.seq', ...
'videos/set00/V012.seq', 'videos/set00/V013.seq','videos/set00/V014.seq', ...
'videos/set01/V000.seq', 'videos/set01/V001.seq','videos/set01/V002.seq', 'videos/set01/V003.seq','videos/set01/V004.seq', 'videos/set01/V005.seq', ...
'videos/set02/V000.seq', 'videos/set02/V001.seq','videos/set02/V002.seq', 'videos/set02/V003.seq','videos/set02/V004.seq', 'videos/set02/V005.seq', ...
'videos/set02/V006.seq', 'videos/set02/V007.seq','videos/set02/V008.seq', 'videos/set02/V009.seq','videos/set02/V010.seq', 'videos/set02/V011.seq', ...
'videos/set03/V000.seq', 'videos/set03/V001.seq','videos/set03/V002.seq', 'videos/set03/V003.seq','videos/set03/V004.seq', 'videos/set03/V005.seq', ...
'videos/set03/V006.seq', 'videos/set03/V007.seq','videos/set03/V008.seq', 'videos/set03/V009.seq','videos/set03/V010.seq', 'videos/set03/V011.seq', ...
'videos/set03/V012.seq', ...
'videos/set04/V000.seq', 'videos/set04/V001.seq','videos/set04/V002.seq', 'videos/set04/V003.seq','videos/set04/V004.seq', 'videos/set04/V005.seq', ...
'videos/set04/V006.seq', 'videos/set04/V007.seq','videos/set04/V008.seq', 'videos/set04/V009.seq','videos/set04/V010.seq', 'videos/set04/V011.seq', ...
'videos/set05/V000.seq', 'videos/set05/V001.seq','videos/set05/V002.seq', 'videos/set05/V003.seq','videos/set05/V004.seq', 'videos/set05/V005.seq', ...
'videos/set05/V006.seq', 'videos/set05/V007.seq','videos/set05/V008.seq', 'videos/set05/V009.seq','videos/set05/V010.seq', 'videos/set05/V011.seq', ...
'videos/set05/V012.seq', ...
'videos/set06/V000.seq', 'videos/set06/V001.seq','videos/set06/V002.seq', 'videos/set06/V003.seq','videos/set06/V004.seq', 'videos/set06/V005.seq', ...
'videos/set06/V006.seq', 'videos/set06/V007.seq','videos/set06/V008.seq', 'videos/set06/V009.seq','videos/set06/V010.seq', 'videos/set06/V011.seq', ...
'videos/set06/V012.seq', 'videos/set06/V013.seq','videos/set06/V014.seq','videos/set06/V015.seq', 'videos/set06/V016.seq','videos/set06/V017.seq','videos/set06/V018.seq', ...
'videos/set07/V000.seq', 'videos/set07/V001.seq','videos/set07/V002.seq', 'videos/set07/V003.seq','videos/set07/V004.seq', 'videos/set07/V005.seq', ...
'videos/set07/V006.seq', 'videos/set07/V007.seq','videos/set07/V008.seq', 'videos/set07/V009.seq','videos/set07/V010.seq', 'videos/set07/V011.seq', ...
'videos/set08/V000.seq', 'videos/set08/V001.seq','videos/set08/V002.seq', 'videos/set08/V003.seq','videos/set08/V004.seq', 'videos/set08/V005.seq', ...
'videos/set08/V006.seq', 'videos/set08/V007.seq','videos/set08/V008.seq', 'videos/set08/V009.seq','videos/set08/V010.seq', ...
'videos/set09/V000.seq', 'videos/set09/V001.seq','videos/set09/V002.seq', 'videos/set09/V003.seq','videos/set09/V004.seq', 'videos/set09/V005.seq', ...
'videos/set09/V006.seq', 'videos/set09/V007.seq','videos/set09/V008.seq', 'videos/set09/V009.seq','videos/set09/V010.seq', 'videos/set09/V011.seq'}, ...
{'videos/set10/V000.seq', 'videos/set10/V001.seq','videos/set10/V002.seq', 'videos/set10/V003.seq','videos/set10/V004.seq', 'videos/set10/V005.seq', ...
'videos/set10/V006.seq', 'videos/set10/V007.seq','videos/set10/V008.seq', 'videos/set10/V009.seq','videos/set10/V010.seq', 'videos/set10/V011.seq'} ...
};
vbbList={ ...
{'annotations/set00/V000.vbb', 'annotations/set00/V001.vbb', 'annotations/set00/V002.vbb', 'annotations/set00/V003.vbb', 'annotations/set00/V004.vbb', 'annotations/set00/V005.vbb', ...
'annotations/set00/V006.vbb', 'annotations/set00/V007.vbb', 'annotations/set00/V008.vbb', 'annotations/set00/V009.vbb', 'annotations/set00/V010.vbb', 'annotations/set00/V011.vbb', ...
'annotations/set00/V012.vbb', 'annotations/set00/V013.vbb', 'annotations/set00/V014.vbb', ...
'annotations/set01/V000.vbb', 'annotations/set01/V001.vbb', 'annotations/set01/V002.vbb', 'annotations/set01/V003.vbb', 'annotations/set01/V004.vbb', 'annotations/set01/V005.vbb', ...
'annotations/set02/V000.vbb', 'annotations/set02/V001.vbb', 'annotations/set02/V002.vbb', 'annotations/set02/V003.vbb', 'annotations/set02/V004.vbb', 'annotations/set02/V005.vbb', ...
'annotations/set02/V006.vbb', 'annotations/set02/V007.vbb', 'annotations/set02/V008.vbb', 'annotations/set02/V009.vbb', 'annotations/set02/V010.vbb', 'annotations/set02/V011.vbb', ...
'annotations/set03/V000.vbb', 'annotations/set03/V001.vbb', 'annotations/set03/V002.vbb', 'annotations/set03/V003.vbb', 'annotations/set03/V004.vbb', 'annotations/set03/V005.vbb', ...
'annotations/set03/V006.vbb', 'annotations/set03/V007.vbb', 'annotations/set03/V008.vbb', 'annotations/set03/V009.vbb', 'annotations/set03/V010.vbb', 'annotations/set03/V011.vbb', ...
'annotations/set03/V012.vbb', ...
'annotations/set04/V000.vbb', 'annotations/set04/V001.vbb', 'annotations/set04/V002.vbb', 'annotations/set04/V003.vbb', 'annotations/set04/V004.vbb', 'annotations/set04/V005.vbb', ...
'annotations/set04/V006.vbb', 'annotations/set04/V007.vbb', 'annotations/set04/V008.vbb', 'annotations/set04/V009.vbb', 'annotations/set04/V010.vbb', 'annotations/set04/V011.vbb', ...
'annotations/set05/V000.vbb', 'annotations/set05/V001.vbb', 'annotations/set05/V002.vbb', 'annotations/set05/V003.vbb', 'annotations/set05/V004.vbb', 'annotations/set05/V005.vbb', ...
'annotations/set05/V006.vbb', 'annotations/set05/V007.vbb', 'annotations/set05/V008.vbb', 'annotations/set05/V009.vbb', 'annotations/set05/V010.vbb', 'annotations/set05/V011.vbb', ...
'annotations/set05/V012.vbb', ...
'annotations/set06/V000.vbb', 'annotations/set06/V001.vbb', 'annotations/set06/V002.vbb', 'annotations/set06/V003.vbb', 'annotations/set06/V004.vbb', 'annotations/set06/V005.vbb', ...
'annotations/set06/V006.vbb', 'annotations/set06/V007.vbb', 'annotations/set06/V008.vbb', 'annotations/set06/V009.vbb', 'annotations/set06/V010.vbb', 'annotations/set06/V011.vbb', ...
'annotations/set06/V012.vbb', 'annotations/set06/V013.vbb', 'annotations/set06/V014.vbb', 'annotations/set06/V015.vbb', 'annotations/set06/V016.vbb', 'annotations/set06/V017.vbb', 'annotations/set06/V018.vbb', ...
'annotations/set07/V000.vbb', 'annotations/set07/V001.vbb', 'annotations/set07/V002.vbb', 'annotations/set07/V003.vbb', 'annotations/set07/V004.vbb', 'annotations/set07/V005.vbb', ...
'annotations/set07/V006.vbb', 'annotations/set07/V007.vbb', 'annotations/set07/V008.vbb', 'annotations/set07/V009.vbb', 'annotations/set07/V010.vbb', 'annotations/set07/V011.vbb', ...
'annotations/set08/V000.vbb', 'annotations/set08/V001.vbb', 'annotations/set08/V002.vbb', 'annotations/set08/V003.vbb', 'annotations/set08/V004.vbb', 'annotations/set08/V005.vbb', ...
'annotations/set08/V006.vbb', 'annotations/set08/V007.vbb', 'annotations/set08/V008.vbb', 'annotations/set08/V009.vbb', 'annotations/set08/V010.vbb', ...
'annotations/set09/V000.vbb', 'annotations/set09/V001.vbb', 'annotations/set09/V002.vbb', 'annotations/set09/V003.vbb', 'annotations/set09/V004.vbb', 'annotations/set09/V005.vbb', ...
'annotations/set09/V006.vbb', 'annotations/set09/V007.vbb', 'annotations/set09/V008.vbb', 'annotations/set09/V009.vbb', 'annotations/set09/V010.vbb', 'annotations/set09/V011.vbb'}, ...
{'annotations/set10/V000.vbb', 'annotations/set10/V001.vbb', 'annotations/set10/V002.vbb', 'annotations/set10/V003.vbb', 'annotations/set10/V004.vbb', 'annotations/set10/V005.vbb', ...
'annotations/set10/V006.vbb', 'annotations/set10/V007.vbb', 'annotations/set10/V008.vbb', 'annotations/set10/V009.vbb', 'annotations/set10/V010.vbb', 'annotations/set10/V011.vbb'} ...
};

Looking forward to your reply.

Thanks and Regards,

Ganesh

Part Number:AM4372

Tool/software: Linux

I have a new AM437x based design that I am trying to troubleshoot. It looks like there are some signal inegrity issues with the SD card interface, so I am trying to boot from UART0. I seem to be able to download the pre-compiled SPL image using XMODEM but that is as far as I get. I do not see anything being printed on UART0 after the XMODEM download completes. Should I be seeing anything on UART0 at this point? 

My design is based partly on the the AM437x EVM but I had to move pins around in order to get the capabilities I needed for my design.  I assume because I do not have the ID EEPROM in my design, that is why i am having issues loading u-boot.

I have the SDK installed and I am able to compile code. I also have  the hardcode EEPROM patch code that I could install. Would doing this get me any further?

Reviewing the training section, I found some information on board porting, but it does not seem to be easily applied to a AM437x design.

http://processors.wiki.ti.com/index.php/Sitara_Linux_Training:_UBoot_Board_Port

https://training.ti.com/intro-linux-board-port-sitara-series

Part Number:TMDSLCDK6748

Tool/software: TI-RTOS

I purchased TMDSLCDK6748 evaluation kit.

My goal is to read/write a file to USB thumb drive through USB1.1 port.

I simply downloaded and rebuild C6748_StarterWare_1_20_04_01/build/c674x/cgt_ccs/c6748/evmC6748/usb_host_msc

Flash the board using CCS8.3 on Windows.

I have connected 2GB thumbdrive (FAT32) to USB1.1 host port.

I can type ls, pwd, etc via teraterm but it always returns "Command returned error code FR_NOT_READY". It looks like USB thumb drive is not detected.

By the way, is USB1.1 is USB0 or USB1?

Any help will be greatly appreciated.

Part Number:AM3352

We have an existing AM3352 based product, containing 1.5V DDR3 SDRAM, which uses the TPS65910A3 PMIC.  We also utilize the battery-backed RTC built into the TPS65910A3.

The 1.5V DDR3 is becoming more difficult to obtain, and 1.35V DDR3L SDRAM appears to be more plentiful. So we're thinking about changing to DDR3L.  It appears the AM3352 supports DDR3L.

Looking at the TPS65910 datasheet, this PMIC doesn't appear to have an option for powering 1.35V DDR.  Is that correct - am I reading that right?  Is there a footprint-compatible part that does provide 1.35V for DDR3L?  If not, what PMIC is recommended (ideally, one also containing a battery-backed RTC)?

Many thanks. 

Part Number:TMS320C5545

Tool/software: Code Composer Studio

In THE 3.6.1-1 the emulator means the on board emulator of c5545?

Part Number:AM5718

A customer is trying to determine the power rating of resistor R807 in the AM571x IDK.  The BOM is provided in .pdf format here:

http://www.ti.com/tool/tmdxidk5718

but R807 is missing.  It probably was cut-off in either row 88 or 98, which were truncated due to row height in the original spreadsheet seemingly.

Is it possible to get the original Excel file for the BOM?

Thank you and regards,

David

Part Number:TDA2

To achieve 32 channel radar we are putting two of the TDA2 Cascade Radar hosts together. TI has recommended these two TDA2 chips are connected together by PCI-e to facilitate synchronization for all 32 channels. Will it be possible to pass a AWR1243 4 channel VIP frame between the two TDA2 chips to process data in the center channel? 

Part Number:TMS320C6652

Hi Champs

The PCIECLKP/N and MCMCLKP/N pins of C6652 are reserved.
So, could you please let me know whether I can leave these pins unconnected or not?
If not, do I have to follow the connection that is described in SPRABI2C( Hardware Design Guide for KeyStone I Devices), p.36 Figure 13?
I'd like to make sure of it.

Best regards,
J-breeze

Part Number:AM4376

Tool/software: Linux

Hello

I used sdk (ti-processor-sdk-linux-am437x-evm-05.00.00.15-Linux-x86-Install.bin)

failed to start weston :

weston log :

Date: 2019-02-25 UTC
[16:08:19.126] weston 2.0.0
               http://wayland.freedesktop.org
               Bug reports to: bugs.freedesktop.org/enter_bug.cgi
               Build: 1.99.94-2-g4c4f13d configure.ac: bump to version 2.0.0 for the official release (2017-02-24 16:19:03 -0800)
[16:08:19.126] Command line: weston --idle-time=0
[16:08:19.126] OS: Linux, 4.14.40-g4796173fc5, #5 PREEMPT Fri Feb 22 15:34:36 CST 2019, armv7l
[16:08:19.128] Using config file '/etc//weston.ini'
[16:08:19.132] Output repaint window is 7 ms maximum.
[16:08:19.143] Loading module '/usr/lib/libweston-2/drm-backend.so'
[16:08:19.152] initializing drm backend
[16:08:19.171] using /dev/dri/card0
[16:08:19.175] Loading module '/usr/lib/libweston-2/gl-renderer.so'
failed to load module: /usr/lib/gbm/gbm_dri.so: cannot open shared object file: No such file or directory
failed to load module: /usr/lib/gbm/gbm_gallium_drm.so: cannot open shared object file: No such file or directory
loaded module : gbm_pvr.so
found valid GBM backend : gbm_pvr.so
[16:08:19.275] warning: either no EGL_EXT_platform_base support or specific platform support; falling back to eglGetDisplay.
[16:08:19.285] failed to initialize display
[16:08:19.285] EGL error state: EGL_BAD_ALLOC (0x3003)
[16:08:19.285] failed to initialize egl
[16:08:19.302] fatal: failed to create compositor backend
PVR:(Error): OpenServices: PVRDRMOpenRender failed [0, ]
PVR:(Error): PVRSRVConnect: Unable to open connection. [0, ]
PVR:(Error): Couldn't connect to services [0, ]

root@am437x-evm:/usr/bin# modetest
trying to open device 'i915'...failed
trying to open device 'amdgpu'...failed
trying to open device 'radeon'...failed
trying to open device 'nouveau'...failed
trying to open device 'vmwgfx'...failed
trying to open device 'omapdrm'...done
Encoders:
id    crtc    type    possible crtcs    possible clones    
34    38    TMDS    0x00000001    0x00000000

Connectors:
id    encoder    status        name        size (mm)    modes    encoders
35    34    connected    DPI-1              0x0        1    34
  modes:
    name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
  800x600 56 800 824 896 1024 600 601 603 625 36000 flags: nhsync, nvsync; type: preferred, driver
  props:
    1 EDID:
        flags: immutable blob
        blobs:

        value:
    2 DPMS:
        flags: enum
        enums: On=0 Standby=1 Suspend=2 Off=3
        value: 0
    5 link-status:
        flags: enum
        enums: Good=0 Bad=1
        value: 0

CRTCs:
id    fb    pos    size
38    49    (0,0)    (800x600)
  800x600 56 800 824 896 1024 600 601 603 625 36000 flags: nhsync, nvsync; type: preferred, driver
  props:
    30 background:
        flags: range
        values: 0 16777215
        value: 0
    31 trans-key-mode:
        flags: enum
        enums: disable=0 gfx-dst=1 vid-src=2
        value: 0
    32 trans-key:
        flags: range
        values: 0 16777215
        value: 0
    33 alpha_blender:
        flags: range
        values: 0 1
        value: 0
    27 zorder:
        flags: range
        values: 0 2
        value: 0

Planes:
id    crtc    fb    CRTC x,y    x,y    gamma size    possible crtcs
36    38    49    0,0        0,0    0           0x00000001
  formats: RX12 AR12 RG16 XR24 RG24 AR24 RA24 RX24
  props:
    6 type:
        flags: immutable enum
        enums: Overlay=0 Primary=1 Cursor=2
        value: 1
    27 zorder:
        flags: range
        values: 0 2
        value: 0
    37 zpos:
        flags: range
        values: 0 2
        value: 0
    28 global_alpha:
        flags: range
        values: 0 255
        value: 255
    29 pre_mult_alpha:
        flags: range
        values: 0 1
        value: 0
39    0    0    0,0        0,0    0           0x00000001
  formats: XR24 RG24 RX12 RG16 YUYV UYVY
  props:
    6 type:
        flags: immutable enum
        enums: Overlay=0 Primary=1 Cursor=2
        value: 0
    27 zorder:
        flags: range
        values: 0 2
        value: 1
    40 zpos:
        flags: range
        values: 0 2
        value: 1
    28 global_alpha:
        flags: range
        values: 0 255
        value: 255
    29 pre_mult_alpha:
        flags: range
        values: 0 1
        value: 0
43    0    0    0,0        0,0    0           0x00000001
  formats: RX12 AR12 RG16 XR24 RG24 YUYV UYVY AR24 RA24 RX24
  props:
    6 type:
        flags: immutable enum
        enums: Overlay=0 Primary=1 Cursor=2
        value: 0
    27 zorder:
        flags: range
        values: 0 2
        value: 2
    44 zpos:
        flags: range
        values: 0 2
        value: 2
    28 global_alpha:
        flags: range
        values: 0 255
        value: 255
    29 pre_mult_alpha:
        flags: range
        values: 0 1
        value: 0

Frame buffers:
id    size    pitch

Part Number:TMS320DM8127

Hi,

My customer tried to change the value of ERDES_TXCFG0.DEEMP, but there is no change on the PCIe output.

I found similar issue in forum at .

Would you pls kindly help again?