Part Number:AM3352
Hello sir,
We have plan to use AM3352 with PCM4201 ADC in Audio Encoder project.
The PCM4201 outputs has 24-bit linear PCM audio data.
Whether MCASP interface of AM3352 support 24-Bit Linear PCM Output Data format of PCM4201 ADC ?
If above condition is possible, then how to connect PCM4201 ADC pins ( DATA, FSYNC, BCK, SCKI ) with AM3352 ?
Regards
Lakshmanan V
Part Number:TMS320C6654
Hi,
The customer is now designing a heat sink for C6657. Could you tell us what the maximum pressure (load force) of this device is ?
I found the similar question about AM5728 below. How about C6657 ?
Thanks and regards,
Hideaki
Part Number:TDA3
Hello,
Is there TDA2X, TDA3x introduction and development process information, materials like PPT, especially focusing on the basic development process, my customer has been evaluating the test platform.
This matter is very important to customers, and it is also urgent, could sent to my email if available, thank you!
Part Number:TDA2PXEVM
I am creating algplugin on dsp2 which takes input from Sync and gives output to Dup . While creating I am getting linking issues in building. But when I put the same algplugin on dsp1 it is getting build correctly as well as object files are also created in binary. I am not able to understand what is getting wrong for dsp2.
Part Number:DRA72
Tool/software: Linux
Hi,experts,
We have a customer board, that used TJA1101 PHY which is the MII interface.
How to modify the driver to support TJA1101 in VSDK ?
1. For linux, how to add TJA1101 support ?
2. NDK, how to add TJA1101 support
Thanks,
Widic
Part Number:AM4372
Tool/software: TI-RTOS
Hi .
#1. I notice there are 2 folder:
C:\TI\pdk_am437x_1_0_13\packages\ti\board\utils\uniflash
C:\TI\pdk_am437x_1_0_13\packages\ti\board\utils\uartAppLoader
What's the purpose of those 2 folder?
#2. If we want to uniflash to flash the customer PCB, we need to make the "uniflash" folder, right?
So, how is the exactly command for building the QSPI Flash boot loader for Uniflash working on AM437?
#3. I type the command as below, but it will show me the error, how to solve?
C:\TI\pdk_am437x_1_0_13\packages\ti\board\utils\uniflash>gmake SOC=AM437x
compiling C:/TI/pdk_am437x_1_0_13/packages/ti/starterware/soc/armv7a/gcc/sbl_init.S ...
linking C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/obj/idkAM572x/xmodem.o C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/obj/idkAM572x/u
art_main.o C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/obj/idkAM572x/qspi.o C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/obj/idkAM572x/
soc.o C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/obj/idkAM572x/sbl_init.ao into C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/bin/idkAM
572x/uart_idkAM572x_flash_programmer.out ...
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/soc/am572x/linker.cmd: No such file or directory
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/board/lib/idkAM572x/a9/release/ti.board.aa9fg: No such file or directory
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/drv/uart/lib/am572x/a9/release/ti.drv.uart.aa9fg: No such file or directory
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/drv/spi/lib/am572x/a9/release/ti.drv.spi.aa9fg: No such file or directory
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/csl/lib/am572x/a9/release/ti.csl.aa9fg: No such file or directory
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/osal/lib/nonos/am572x/a9/release/ti.osal.aa9fg: No such file or directory
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/board/lib/idkAM572x/a9/release/ti.board.aa9fg: No such file or directory
gmake: *** [C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/bin/idkAM572x/uart_idkAM572x_flash_programmer.out] Error 1
C:\TI\pdk_am437x_1_0_13\packages\ti\board\utils\uniflash>
BR Rio
Part Number:AM5716
Hi Experts,
I'd like to identify that WDT_RST is occurred when AM571x is reset. However, due to the circuit that avoids Errata i862, it seems that PRM_RSTST is always '1' (GLOBAL_COLD_RST) after any resets.
Do you have a good way to identify WDT_RST? Also, what does the following method described in Errata specifically mean? What should I do?
"To maintain some visibility software may be able to store information in PMIC BACKUP or other PMIC registers."
Regards,
Kzk
Part Number:AM5728
Tool/software: Code Composer Studio
Hi,
I want to run the No OS (Bare Metal) Example on the MINI5728.
After I right click CortexA15_0 and select connect target., CCS prompts that Break at address "0x3f9f0" with no debug information available, or outside of program code.
Console prints the following information：
Cortex_M4_IPU1_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<--- Cortex_M4_IPU1_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<--- Cortex_M4_IPU1_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<--- Cortex_M4_IPU1_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<--- C66xx_DSP1: GEL Output: --->>> AM572x C66x DSP Startup Sequence In Progress... <<<--- C66xx_DSP1: GEL Output: --->>> AM572x C66x DSP Startup Sequence DONE! <<<--- C66xx_DSP2: GEL Output: --->>> AM572x C66x DSP Startup Sequence In Progress... <<<--- C66xx_DSP2: GEL Output: --->>> AM572x C66x DSP Startup Sequence DONE! <<<--- CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence In Progress... <<<--- CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence DONE! <<<--- CortexA15_1: GEL Output: --->>> AM572x Cortex A15 Startup Sequence In Progress... <<<--- CortexA15_1: GEL Output: --->>> AM572x Cortex A15 Startup Sequence DONE! <<<--- IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<--- CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress... CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<---- CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> --- CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<---- CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do. CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<--- CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<--- CortexA15_0: GEL Output: --->>> I2C Init <<<--- CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> AM572x PG1.1 GP device <<<--- CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<--- CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking... CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE! CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: PER DPLL already locked, now unlocking CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE! CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking.... CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE! CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE! CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<--- CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress... CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE! CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers CortexA15_0: GEL Output: as per HW leveling output CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from CortexA15_0: GEL Output: PHY_STATUSx registers CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers CortexA15_0: GEL Output: as per HW leveling output CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from CortexA15_0: GEL Output: PHY_STATUSx registers CortexA15_0: GEL Output: Two EMIFs in interleaved mode - (2GB total) CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<---- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<--- CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!! <<<--- CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<---- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---
How should I solve this problem?
Thank you!
Part Number:DRA72
Tool/software: Linux
The customer want to add TJA1101 support in VSDK0305. The default is RGMII, but the customer board interface is MII. I checked in E2E, and found similar issue as below link.
Please check and give some suggestions how to modify the driver to add TJA1101 support in VSDK0304?
First we can add support in linux? then we can porting to NDK.
Best Regards,
Fredy
Part Number:AM3352
Tool/software: TI-RTOS
Hi Champs,
We would like to insert Bus switch (SN74CBT3244C) between SD card and AM3352 (MMC/SD out put pins) .
This bus switch purpose is to prevent reverse current to AM335x side when Device power is shout down unexpectedly.
We are trying to consider "delay" on the Bus switch.
However, if between MMC0_CLK and MMC_CMD/DAT occur "delay", Can we control this delay on the AM3352 ?
If so, could you please tell us this resolution.
Regards,
Kz777
Part Number:TMS320C6748
Tool/software: Code Composer Studio
Good afternoon sir,
Sir, when iam connecting myError connecting to the target:
(Error -151 @ 0x0) tms320c6748 kit to my pc , iam getting the following error,
please help me hoe to resolve this problem
One of the FTDI driver functions used during
the connect returned bad status or an error.
The cause may one or more of: invalid emulator serial number,
blank emulator EEPROM, missing FTDI drivers, faulty USB cable.
Use the xds100serial command-line utility in the 'common/uscif'
folder to verify the emulator can be located.
(Emulation package 5.0.872.0)
Part Number:AM4376
Hi,
I have a question of the Switching Characteristics of AM437x.
Looking at the revision history of the AM437x datasheet (SPRS851E), There is description "Removed Rise time, Fall time, and Transition time in all Switching Characteristics", but for what reason were they deleted?
From now on, what data should be used as a reference to design the circuit?
Also, please let me know if you have actual value data of switching characteristics.
Best regards,
Part Number:TMS320C6748
Tool/software: Code Composer Studio
Error connecting to the target:
(Error -151 @ 0x0)
One of the FTDI driver functions used during
the connect returned bad status or an error.
The cause may one or more of: invalid emulator serial number,
blank emulator EEPROM, missing FTDI drivers, faulty USB cable.
Use the xds100serial command-line utility in the 'common/uscif'
folder to verify the emulator can be located.
(Emulation package 5.0.872.0)
Part Number:TDA2PXEVM
Tool/software: TI-RTOS
Hi All,
I am working on VSDK 3.05. I am working on a decoder which takes data from 4 cameras and sends the data on the 2 lanes of CSI2 PHY2 with the resolution 640x480.
As the decoder contains an ISP I am not using M2mIspLink and Alg_IssAewb. The use case contains Capture + Display. I am having issues in setting display params.
I am refering to the use case iss_capture_isp_simcop_display.
My doubt is in the function UseCase_SetAppPrms().As M2mIsp link is not used I have not used the following variables in my use case object.
IssM2mSimcopLink_ConfigParams simcopConfig;
vpsissldcConfig_t ldcCfg;
vpsissvtnfConfig_t vtnfCfg;
IssM2mSimcopLink_OperatingMode simcopMode;
Bool bypassVtnf;
Bool bypassLdc;
Due to this I have not set simcopMode, bypassVtnf,, bypassLdc in function UseCase_SetAppPrms() .
Will this create any issues, as I do not have the decoder with me right now,I cannot test it.So just wanted to ask whether this is fine or not?
Regards,
Deepika
Part Number:AM5K2E02
Hi,
We are testing a custom PCB with a AM5K2E02 SOC.
We are having trouble booting from the NAND flash device (S34MS01G200TFV000). I can verify using debugger that the boot pins are set correctly for booting from NAND Flash. I have been able to boot over UART too. Also I can read/write from the NAND flash using nandwriter program running on the AM5K2E02.
So my question is, is there any reason this part S34MS01G200TFV000 would be incompatible with the AM5K2E02 Bootloader?
Also is there a test image in GP header format that I can use to ensure the boot procedure is working correctly, even just for comparison? We are currently writing our own test program to the flash.
Thanks,
Jasvinder
Part Number:DRA74
Tool/software: Linux
In our system , VIS version " REL.VIS.01.50.23.01" , we have some test on APPE algorithm.We change Ch distribution from 5.1to 7.1（CHAN_CFG_8CHANNEL_SURROUND2）. But in "per-channel EQ " test ; and two of eight CHs（Ls & Rb）,the only fifth frequency band (about 512Hz ) , EQ don't work ,other bands are OK .Parameters we set on the RadioApp command line. I readback theparameter (I have writen) is OK by command line tool .
Part Number:AM4376
Tool/software: Linux
Hello
I use Ti SDK (ti-processor-sdk-linux-am437x-evm-05.00.00.15)
failed to weston boot .
weston log :
Date: 2019-02-25 UTC
[16:08:19.126] weston 2.0.0
http://wayland.freedesktop.org
Bug reports to: bugs.freedesktop.org/enter_bug.cgi
Build: 1.99.94-2-g4c4f13d configure.ac: bump to version 2.0.0 for the official release (2017-02-24 16:19:03 -0800)
[16:08:19.126] Command line: weston --idle-time=0
[16:08:19.126] OS: Linux, 4.14.40-g4796173fc5, #5 PREEMPT Fri Feb 22 15:34:36 CST 2019, armv7l
[16:08:19.128] Using config file '/etc//weston.ini'
[16:08:19.132] Output repaint window is 7 ms maximum.
[16:08:19.143] Loading module '/usr/lib/libweston-2/drm-backend.so'
[16:08:19.152] initializing drm backend
[16:08:19.171] using /dev/dri/card0
[16:08:19.175] Loading module '/usr/lib/libweston-2/gl-renderer.so'
failed to load module: /usr/lib/gbm/gbm_dri.so: cannot open shared object file: No such file or directory
failed to load module: /usr/lib/gbm/gbm_gallium_drm.so: cannot open shared object file: No such file or directory
loaded module : gbm_pvr.so
found valid GBM backend : gbm_pvr.so
[16:08:19.275] warning: either no EGL_EXT_platform_base support or specific platform support; falling back to eglGetDisplay.
[16:08:19.285] failed to initialize display
[16:08:19.285] EGL error state: EGL_BAD_ALLOC (0x3003)
[16:08:19.285] failed to initialize egl
[16:08:19.302] fatal: failed to create compositor backend
PVR:(Error): OpenServices: PVRDRMOpenRender failed [0, ]
PVR:(Error): PVRSRVConnect: Unable to open connection. [0, ]
PVR:(Error): Couldn't connect to services [0, ]
test : insert usb mouse did not succeed.
root@am437x-evm:/usr/bin# modetest
trying to open device 'i915'...failed
trying to open device 'amdgpu'...failed
trying to open device 'radeon'...failed
trying to open device 'nouveau'...failed
trying to open device 'vmwgfx'...failed
trying to open device 'omapdrm'...done
Encoders:
id crtc type possible crtcs possible clones
34 38 TMDS 0x00000001 0x00000000
Connectors:
id encoder status name size (mm) modes encoders
35 34 connected DPI-1 0x0 1 34
modes:
name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
800x600 56 800 824 896 1024 600 601 603 625 36000 flags: nhsync, nvsync; type: preferred, driver
props:
1 EDID:
flags: immutable blob
blobs:
value:
2 DPMS:
flags: enum
enums: On=0 Standby=1 Suspend=2 Off=3
value: 0
5 link-status:
flags: enum
enums: Good=0 Bad=1
value: 0
CRTCs:
id fb pos size
38 49 (0,0) (800x600)
800x600 56 800 824 896 1024 600 601 603 625 36000 flags: nhsync, nvsync; type: preferred, driver
props:
30 background:
flags: range
values: 0 16777215
value: 0
31 trans-key-mode:
flags: enum
enums: disable=0 gfx-dst=1 vid-src=2
value: 0
32 trans-key:
flags: range
values: 0 16777215
value: 0
33 alpha_blender:
flags: range
values: 0 1
value: 0
27 zorder:
flags: range
values: 0 2
value: 0
Planes:
id crtc fb CRTC x,y x,y gamma size possible crtcs
36 38 49 0,0 0,0 0 0x00000001
formats: RX12 AR12 RG16 XR24 RG24 AR24 RA24 RX24
props:
6 type:
flags: immutable enum
enums: Overlay=0 Primary=1 Cursor=2
value: 1
27 zorder:
flags: range
values: 0 2
value: 0
37 zpos:
flags: range
values: 0 2
value: 0
28 global_alpha:
flags: range
values: 0 255
value: 255
29 pre_mult_alpha:
flags: range
values: 0 1
value: 0
39 0 0 0,0 0,0 0 0x00000001
formats: XR24 RG24 RX12 RG16 YUYV UYVY
props:
6 type:
flags: immutable enum
enums: Overlay=0 Primary=1 Cursor=2
value: 0
27 zorder:
flags: range
values: 0 2
value: 1
40 zpos:
flags: range
values: 0 2
value: 1
28 global_alpha:
flags: range
values: 0 255
value: 255
29 pre_mult_alpha:
flags: range
values: 0 1
value: 0
43 0 0 0,0 0,0 0 0x00000001
formats: RX12 AR12 RG16 XR24 RG24 YUYV UYVY AR24 RA24 RX24
props:
6 type:
flags: immutable enum
enums: Overlay=0 Primary=1 Cursor=2
value: 0
27 zorder:
flags: range
values: 0 2
value: 2
44 zpos:
flags: range
values: 0 2
value: 2
28 global_alpha:
flags: range
values: 0 255
value: 255
29 pre_mult_alpha:
flags: range
values: 0 1
value: 0
Frame buffers:
id size pitch
Part Number:PERFAUDIO-FIRMWARE-DA8XX
Tool/software: TI-RTOS
Hi All,
I am working on DA830 chip where, i use a flash stick (sandisk 16GB) to store the output data. I am using only DSP core in DA830. I used an example(USBHostMSC) in pdk_omapl137 to read and write to usb device. Now the problem is the program runs fine but, after some time it gets stuck in this function "EventCombiner_dispatch()". The program is in an infinite loop in this function.
can you please help me solve this problem.
Regards,
surya
Part Number:TCI6630K2L
Tool/software: TI-RTOS
Hi,
I am trying to run my application in IPV6 environment. Trying to send packet out from DSP core but cant see any packet getting out using wireshark.
Same application works fine in Ipv4 env.
I captured netfp status for the same as below :
"C1 number failed table matched: 5769"
Setup & Hw env
LAMARR "K2L"
"pdk_keystone2_3_01_02_05" "syslib_3_00_09_00"
Can you please let me know, what can be wrong.
All configured IPV6 ip are pingable from board.
----------------NetFP Global stats---------------------------
inUdpDatagrams: 0
inIpEspPkt: 0
inIpDelivers: 0
inIpHdrErrors: 0
inIpReceives: 5769
inIpOctets: 0
inIpReasmOk: 0
inIpReasmFails: 0
inIpReasmReqd: 0
outUdpDatagrams: 113293
outIpDiscards: 0
outIpFragsOk: 0
outIpOctets: 32757346
outIpDatagrams: 113293
-------------------------------------------------------------
-----------------------PA Stats------------------------------
C1 number of packets: 131196
C1 number IPv4 packets: 84
C1 number Inner IPv4 packets: 0
C1 number IPv6 packets: 5685
C1 number Inner IPv6 packets: 0
C1 number custom packets: 0
C1 number SRIO packets : 0
C1 number llc/snap fail: 0
C1 number table matched: 6014
C1 number failed table matched: 5769
C1 number IP frags: 0
C1 number IP depth overflow: 0
C1 number vlan depth overflow: 0
C1 number gre depth overflow: 0
C1 number mpls packets: 0
C1 number of parse fail: 0
C1 number invalid IPv6 opts: 0
C1 number of silent discard: 0
C1 number of invalid control: 0
C1 number of invalid states: 0
C1 number of system fails: 0
C2 number of packets: 1
C2 number of UDP packets: 0
C2 number of TCP packets: 0
C2 number of custom packets: 0
C2 number of silent discard: 0
Thanks .
