Hello,

(Target OS : Android Oreo)

(Platform: J6EVM5777)

We are trying to build u-boot source by referring the page

http://omappedia.org/wiki/6AM.1.3_Release_Notes#Flashing_eMMC_images

We are trying to build the u-boot image for the platform XC5777X by using the command

$ make dra7xx_evm_config

We are getting the below error:

make: *** No rule to make target 'dra7xx_evm_config'. Stop.

Since there is no such configuration file in the u-boot directory. Could you help us to resolve this issue?

Thanks in advance

Regards,

Poongundran

Part Number:TMDSDSK6713

Hi I am Ammar from NUST University, Pakistan. I am using DSP kit DSK6713 with COde composer studio version 6. Internal memory is less, so i am putting my .txt data (all text) in SDRAM. But while debugging, it shows error :

TMS320C671X: Trouble Halting Target CPU: Error 0x80000020/-1060 Fatal Error during: Execution, An unknown error prevented the emulator from accessing the processor in a timely fashion. It is recommended to RESET EMULATOR. This will disconnect each target from the emulator. The targets should then be power cycled or hard reset followed by an emureset and reconnect to each target.

Error picture is attached.

Kindly Help

Regards!!

Part Number:AM5728

Tool/software: TI-RTOS

Hi,

I understand that the L1D SRAM on the DSPs is being used by TI-RTOS for caching data. Can I section memory in L1D and use it to store my own data?

Regards,

Shaunak

Part Number:PROCESSOR-SDK-TDAX

Hello Everyone,

I want to merge three different image areas from two seperate cameras into one frame (see attached image). Those areas have seperate LDC mesh tables which are given to us by a third party. I'm using PSDK 3.5 with a custom TDA2P board and two sensors (1920x1080). To begin with I took the usecase 1CH ISS Capture + ISS ISP + ISS LDC+VTNF + Display and I'm planning to extend it with the second sensor.

1. Is it possible to merge these three image areas by only using the SIMCOP? The idea was to run one frame through the simcop 3 times and add one image area to it in every run. So e.g. first run: warp area 1 from cam 1 and copy it to its position on the output frame. Then repeat this with area 2 und 3 while keeping the previous image areas. When all 3 areas are copied, send the frame to the display. Is this possible in the PSDK without changing the majority of data structs/functions and without the use of additional links?

2. When I warp image area 1 and I want to add it to the output frame it changes its effective resolution. For example I only want to copy half of the frame of Cam 1 to the output frame (see attached picture). So my output frame would be 960x1080. However, drvSimcopCfg.ldcCfg.advCfg.outputFrameHeight is always set to the outputFrameHeight of the output frame (1920x1080). This happens in IssM2mSimcopLink_drvSetSimcopConfig. Is there a way to dynamically change the output resolution of the SIMCOP with every run? I dont want it to process a complete full HD frame in every run but just the selected image area.

Regards,

Tobias

Part Number:TDA2PXEVM

Hello,

I am trying to understand the "cascade_radar_object_detect" usecase [path: vision_sdk\apps\src\rtos\radar\src\usecases\cascade_radar_object_detect] and develop my own use-case for cascaded board with 4 AWR1243s with TDA2px using FPD-Link. I had the following questions:

1. In the 'chains_cascadeOd.c' file, for the struct aoa_rxAntOffset_t gAoa_sensorRxOffset[], could you please what do you mean by .sensorAzimOffs? The four values for .sensorAzimOffs are 0,11,50 and 46 and I didn't find any relation between these values? How do you define if we were to design our own cascaded design? Also, what is gAoa_rowToElevationIdx[] in the same program, line 189?

2. How did you calculate the TI RF calibration coefficients defined in the AlgorithmFxn_RadarDspProcessComplexNum gChanCompCoefs []?

I look forward to your reply. Thank you!

Best Regards,

Nishant

Part Number:TMDXICE110

Tool/software: Code Composer Studio

WARNING:     memory region `APP_CACHED_DATA_BLK1_MEM' not declared

Debug Load ERROR:

CortexA15_0: File Loader: Verification failed: Values at address 0x00000000 do not match Please verify target memory and memory map.
CortexA15_0: GEL: File: C:\ti\pdk_am57xx_1_0_13\packages\MyExampleProjects\NIMU_ICSS_BasicExample_idkAM572x_wSocLib_armExampleproject\Debug\NIMU_ICSS_BasicExample_idkAM572x_wSocLib_armExampleproject.out: a data verification error occurred, file load failed.
CortexA15_0: Unable to terminate memory download: NULL buffer pointer at 0x3aa4 (Emulation package 8.0.903.4)(Please visit the site to view this file)

Part Number:TDA2

Hello,

I am trying to figure out the maximum possible 2D and 3D complex FFT size possible using TDA2x and TDA2px  for our application. For the cascaded design that will hopefully be released in the first quarter of 2019 by TI, could you please tell me what is the exact part number of TDA2x that you have used? Based on the datasheet of TDA2X ADAS processors, from Pg 142, TDA2xxT is the best processor to use because it has the fastest DSP and EVE processing speed. Based on pg 6, TDA2SXx and TDA2SGx of TDA2Sxx subfamily is the best processor because it suits all the hardware requirements for supporting 4 AWR1243s together. Also, could you also tell me the max datarate that the videoports of TDA2x can handle? TDA2x has only 3 VIP ports present. Then how do you connect and transfer data from four AWR1243s to the three VIP ports? Could you please give a brief explanation to it?

Thank you!

Best Regards,

Nishant

Part Number:AM3358

Hello,

I have firmware for the AM3358 pru0 which sets up rpmsg communication just like in the software support package RPMsg echo example. According to  , I'm supposed to receive a message from the Linux host in order to determine the src/dst for the buffer to send a message back, which I do. The problem is, I'm sending back a completely arbitrary message:

            while (pru_rpmsg_receive(&transport, &src, &dst, payload, &len) == PRU_RPMSG_SUCCESS) {
                pru_rpmsg_send(&transport, dst, src, "Arbitrary Message", strlen("Arbitrary Message"));
            }

and `/dev/rpmsg_pru30` still echoes back the old message. How do I send a different message back to Linux?

Best regards,
Bartlomiej Nowak

Part Number:TDA2

Hello,

I am trying to understand the fundamental differences between different use-case and develop my own use-case for my application. In the use-case "multi_radar_capture_fft_display," you have used 'ISSCapture' algorithm process to collect CSI-2 data from AWR1243 radar sensor. However, in the use-case "cascade_radar_object_detect", you have used "Capture" algorithm process to collect CSI-2 radar data. What is the fundamental difference between these two processes? Is there any advantage of using one over another?

I look forward to your reply. Thank you!

Best Regards,

Nishant

Part Number:TMS320C6412

Tool/software: TI-RTOS

I am maintaining a set of code that is used by a TMS320C6412 and is currently running the following SW:

• CCS v3.3 (not actively using CCS, only the libraries)
• C6000 packages: CSL, RTDX, CGTOOLS, C6400DSPLIB
• BIOS v5.31.02

The latest load that supports this DSP appears to be DSP/BIOS v5.42.02.10. Would this be the most stable release to upgrade to? Can I anticipate any issues from jumping over so many releases?

Rebuilding the code is no issue and I'm not looking to use any new features. Does Code Composer need to be installed, or can I install the libraries as stand-alone packages?

Part Number:TMS320C6678

Hi,

My customer would like to use GPIO interrupt for input level detection on C6678. But as you know, C6678 only supports edge detection for the interrupt. 
I've already suggested this fact to the customer,  but they still pursue the way how they could realize the level detection with C6678 (maybe including external logic). Do you have any idea for this request ?

Best Regards,
NK

Part Number:DRA71

Tool/software: Linux

hi 

pvrsrvctl  process run correctly when system use 1024M memory.  pvrsrvctl  process occasionally appear  crash error when system use 512M memory. 

Annex   Document of memory_512M_map.xlsx is 512M memory map,

Annex   Documents of _pvrsrvctl_crash.log and pvrsrvctl_crash1.log are  crash log.

(Please visit the site to view this file)(Please visit the site to view this file)(Please visit the site to view this file)

Part Number:TDA3

Tool/software: TI C/C++ Compiler

How can I test memory leak in dsp?I debug the program in debug mode.One statement says free(a);then the program dies and the serial port indicates like below,last sentense says invalid free.But the addr I free is not invalid,is there any good tool I can use to check the memory leak?Thanks!

[DSP2  ]     29.879308 s:  SYSTEM: Heap = LOCAL_L2             @ 0x00800000, Total size = 227264 B (221 KB), Free size = 227264 B (221 KB)
[DSP2  ]     29.879369 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 524288 B (512 KB), Free size = 517304 B (505 KB)
[DSP2  ]     30.337003 s:  z.data_pt = 84801b88
[DSP2  ]     30.337247 s: z_ipl.data_pt is 84802390
[DSP2  ]     30.337278 s: tracker_pt->tmpl.data_pt is 84802390
[DSP2  ]     30.337705 s: tracker_pt->hann.data_pt is 84804398
[DSP2  ]     30.337735 s: hann1t.data_pt is 84801b88
[DSP2  ]     30.337766 s: hann2t.data_pt is 84801c10
[DSP2  ]     30.337796 s: hann2d.data_pt is 848063a0
[DSP2  ]     30.338650 s: tracker_pt->prob.data_pt is 848063a0
[DSP2  ]     30.339382 s: outputtmp2 in createGaussianPeak is 8480a3a8
[DSP2  ]     30.339443 s: outputtmp1 in createGaussianPeak is 8480e3b0
[DSP2  ]     30.339657 s: tracker_pt->alphaf.data_pt is 8480a3a8
[DSP2  ]     30.339687 s: Output.data_pt in Train_Gauss is 8480e3b0
[DSP2  ]     30.339718 s: outputtmp1 in Train_Gauss is 84ae9278
[DSP2  ]     30.339748 s: outputtmp2 in Train_Gauss is 848123b8
[DSP2  ]     30.339840 s: input1_cpl in GuassCorrelation is 848163c0
[DSP2  ]     30.339870 s: input2_cpl in GuassCorrelation is 8481a3c8
[DSP2  ]     30.339901 s: outputtmp1 in GuassCorrelation is 8481e3d0
[DSP2  ]     30.339931 s: outputtmp2 in GuassCorrelation is 848223d8
[DSP2  ]     30.339962 s: output1 in GuassCorrelation is 848263e0
[DSP2  ]     30.339992 s: output2 in GuassCorrelation is 8482a3e8
[EVE1  ]     29.449551 s:  IPC_IN_0   : Create in progress !!!
[EVE1  ]     29.450497 s:  IPC_IN_0   : Create Done !!!
[EVE1  ]     29.451168 s:  ALGORITHM: Create in progress (algId = 16) !!!
[EVE1  ]     29.595437 s:  ALGORITHM: Create Done (algId = 16) !!!
[EVE1  ]     29.596138 s:  IPC_OUT_0   : Create in progress !!!
[EVE1  ]     29.596565 s:  IPC_OUT_0   : Create Done !!!
[EVE1  ]     29.879674 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1023
[EVE1  ]     29.879948 s:  SYSTEM: Heap = LOCAL_L2             @ 0x40020000, Total size = 22528 B (22 KB), Free size = 15684 B (15 KB)
[EVE1  ]     29.880497 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 262144 B (256 KB), Free size = 229264 B (223 KB)
[DSP2  ]     36.136887 s:
[DSP2  ]     36.136918 s:  ### XDC ASSERT - ERROR CALLBACK START ###
[DSP2  ]     36.136948 s:
[DSP2  ]     36.137040 s: assertion failure: A_invalidFree: Invalid free
[DSP2  ]     36.137070 s:
[DSP2  ]     36.137070 s:  ### XDC ASSERT - ERROR CALLBACK END ###
[DSP2  ]     36.137101 s:
[DSP2  ]     36.137192 s: ti.sysbios.heaps.HeapMem: line 428: ti.sysbios.heaps.HeapMem: line 428: assertion failure: A_invalidFree: Invalid free
[DSP2  ]     36.137284 s: xdc.runtime.Error.raise: terminating execution

Part Number:TMS320C6655

Some questions by designing stand-alone data acquisition board using C6655.

Q1) according to datasheet, the normal AVS voltage is 0.85V to 1.1V. But some discusion in E2E states different range as like 0.7 to 1.1 or 0.9 to 1.1.

What is the exact value for design AVS. I'm planning to use LM10011.

Q2) this device have dual function interface EMIF16 and UPP. Is it possible to use both function during normal operation ?

SRAM is connected to EMIF16 and UPP used for data acquisition. In this case, can EDMA transfer the data to SRAM from UPP ?

Best regard,

Sympson

Part Number:TCI6630K2L

Tool/software: Code Composer Studio

Hello,

We have used K2L EVM as reference design to design one of our eNodeB Board. The schematics is same as K2L EVM.

We are trying to load Uboot on the Fresh (New) Board. The processor is out of reset, clocks are fine, We are able to see boot complete on BMC (TIVATM4C129) serial console. But after loading uboot nothing is output on SOC serial console.

We have followed the below link.

https://github.com/qemu/u-boot/blob/master/board/ti/ks2_evm/README

As per the link procedure, we must see some output on SOC Serial Port. The problem is, We are able to access the SOC cores, Load uboot to ARM Core 0 . Once it is done we are not getting any output on the serial console of the SOC. 

Kindly let me know whether the steps we followed is correct? any steps missing. We require to bring up the board with challenging timelines. Kindly advice...

Best Regards,

Sumathi

Tool/software: TI-RTOS

hello.

I have a beaglebone black board and program my device by a sysbios OS. my program included uart and ethernet. That way, by udp from linux, I send a packet to ethernet of beaglebone and respectively to uart of beaglebone.

Now i want to know how amount of time pass during my task...

please help me.

Part Number:PROCESSOR-SDK-AM57X

Tool/software: Linux

Hi,

We are using PROCESSOR-SDK-AM57X ti-processor-sdk-linux-am57xx-evm-05.02.00.10, using UART1 (ttyO0) and customized am571x-idk. Device trees are modifile as per am571x-idk.

Booting through sd card by creating bootable sd card using this(tisdk-rootfs-image-am57xx-evm.tar.xz) tarball, having a problem with kernal booting it stops at starting kernal ......... for a long time and moves forward then regulator and ldo voltages are disabling. Please find the log below.

Kindlly suggest what's wrong.

U-Boot SPL 2018.01-00558-gca1e85ecb5-dirty (Jan 12 2019 - 14:56:01)
DRA722-GP ES1.0

U-Boot SPL 2018.01-00558-gca1e85ecb5-dirty (Jan 12 2019 - 14:56:01)
DRA722-GP ES1.0
Trying to boot from MMC1
no pinctrl state for default mode
no pinctrl state for default mode


U-Boot 2018.01-00558-gca1e85ecb5-dirty (Jan 12 2019 - 14:56:01 +0530)

CPU  : DRA722-GP ES1.0
Model: TI AM5718 IDK
Board: AM571x IDRAM:  1 GiB
MMC:   prop_name: pinctrl-0 mode: default index: 0
prop_name: pinctrl-6 mode: sdr104 index: 6
prop_name: pinctrl-4 mode: sdr50 index: 4
prop_name: pinctrl-5 mode: ddr50 index: 5
prop_name: pinctrl-3 mode: sdr25 index: 3
prop_name: pinctrl-2 mode: sdr12 index: 2
prop_name: pinctrl-1 mode: hs index: 1
prop_name: pinctrl-0 mode: default index: 0
prop_name: pinctrl-2 mode: ddr_1_8v index: 2
prop_name: pinctrl-1 mode: hs index: 1
OMAP SD/MMC: 0, OMAP SD/MMC: 1
Warning: fastboot.board_rev: unknown board revision
GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645
part_get_info_efi: *** ERROR: Invalid GPT ***
GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645
part_get_info_efi: *** ERROR: Invalid Backup GPT ***
SCSI:  SATA link 0 timeout.
AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst
scanning bus for devices...
Found 0 device(s).
Net:   Could not get PHY for ethernet@48484000: addr 0

Warning: ethernet@48484000 using MAC address from ROM
eth0: ethernet@48484000
Hit any key to stop autoboot:  0
WARNING: Could not determine device tree to use
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
** Unable to read file boot.scr **
1490 bytes read in 4 ms (363.3 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc0 ...
Running uenvcmd ...
1 bytes read in 3 ms (0 Bytes/s)
Already setup.
switch to partitions #0, OK
mmc0 is current device
SD/MMC found on device 0
4022784 bytes read in 193 ms (19.9 MiB/s)
92417 bytes read in 20 ms (4.4 MiB/s)
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 8ffe6000, end 8ffff900 ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.14.79-gbde58ab01e (medha@medha) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #2 SMP PREEMPT Fri Jan 19
[    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
[    0.000000] CPU: div instructions available: patching division code
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] OF: fdt: Machine model: TI AM5718 IDK
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
[    0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
[    0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x00000000be400000
[    0.000000] OMAP4: Map 0x00000000bfd00000 to fe600000 for dram barrier
[    0.000000] DRA722 ES1.0
[    0.000000] percpu: Embedded 15 pages/cpu @ef64d000 s31372 r8192 d21876 u61440
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 210496
[    0.000000] Kernel command line: console=ttyO0,115200n8 root=PARTUUID=23d2adc0-02 rw rootfstype=ext4 rootwait
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 644604K/848896K available (8192K kernel code, 347K rwdata, 2564K rodata, 2048K init, 282K bss, 24068K reserved, 180224)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0a00000   (10208 kB)
[    0.000000]       .init : 0xc0e00000 - 0xc1000000   (2048 kB)
[    0.000000]       .data : 0xc1000000 - 0xc1056e98   ( 348 kB)
[    0.000000]        .bss : 0xc1058000 - 0xc109ebe0   ( 283 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.
[    0.000000]  Tasks RCU enabled.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] OMAP clockevent source: timer1 at 32786 Hz
[    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[    0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
[    0.000016] Switching to timer-based delay loop, resolution 162ns
[    0.000353] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000362] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000780] Console: colour dummy device 80x30
[    0.000798] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
[    0.000805] This ensures that you still see kernel messages. Please
[    0.000812] update your kernel commandline.
[    0.000833] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
[    0.000848] pid_max: default: 32768 minimum: 301
[    0.000954] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000967] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001507] CPU: Testing write buffer coherency: ok
[    0.001543] CPU0: Spectre v2: using ICIALLU workaround
[    0.001743] /cpus/cpu@0 missing clock-frequency property
[    0.001757] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.039872] Setting up static identity map for 0x80200000 - 0x80200060
[    0.059876] Hierarchical SRCU implementation.
[    0.080060] EFI services will not be available.
[    0.099932] smp: Bringing up secondary CPUs ...
[    0.099943] smp: Brought up 1 node, 1 CPU
[    0.099952] SMP: Total of 1 processors activated (12.29 BogoMIPS).
[    0.099959] CPU: All CPU(s) started in HYP mode.
[    0.099966] CPU: Virtualization extensions available.
[    0.100399] devtmpfs: initialized
[    0.117291] random: get_random_u32 called from bucket_table_alloc+0x108/0x230 with crng_init=0
[    0.120073] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[    0.120275] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.120292] futex hash table entries: 256 (order: 2, 16384 bytes)
[    0.124033] pinctrl core: initialized pinctrl subsystem
[    0.124520] DMI not present or invalid.
[    0.124766] NET: Registered protocol family 16
[    0.130834] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.131707] omap_hwmod: l3_main_2 using broken dt data from ocp
[    0.323922] cpuidle: using governor ladder
[    0.323957] cpuidle: using governor menu
[    0.331782] OMAP GPIO hardware version 0.1
[    0.356771] No ATAGs?
[    0.356819] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[    0.356833] hw-breakpoint: maximum watchpoint size is 8 bytes.
[    0.357193] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[    0.357204] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[    0.357737] OMAP DMA hardware revision 0.0
[    0.392322] edma 43300000.edma: memcpy is disabled
[    0.395592] edma 43300000.edma: TI EDMA DMA engine driver
[    0.402438] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[    0.404119] V3_3D: supplied by VMAIN
[    0.406744] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[    0.406954] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[    0.407196] omap-iommu 58882000.mmu: 58882000.mmu registered
[    0.407444] omap-iommu 55082000.mmu: 55082000.mmu registered
[    0.409831] palmas 0-0058: Irq flag is 0x00000000
[    0.442624] random: fast init done
[    1.054708] random: crng init done
[   64.182169] irq 166: nobody cared (try booting with the "irqpoll" option)
[   64.182185] CPU: 0 PID: 22 Comm: irq/166-tps6591 Not tainted 4.14.79-gbde58ab01e #2
[   64.182195] Hardware name: Generic DRA72X (Flattened Device Tree)
[   64.182203] Backtrace:
[   64.182225] [<c020b4dc>] (dump_backtrace) from [<c020b7c0>] (show_stack+0x18/0x1c)
[   64.182237]  r7:000000a6 r6:20000193 r5:00000000 r4:c1053d10
[   64.182253] [<c020b7a8>] (show_stack) from [<c0931328>] (dump_stack+0x90/0xa4)
[   64.182272] [<c0931298>] (dump_stack) from [<c02820a4>] (__report_bad_irq+0x30/0xd4)
[   64.182283]  r7:000000a6 r6:c1022048 r5:00000000 r4:ef2ec300
[   64.182297] [<c0282074>] (__report_bad_irq) from [<c0282498>] (note_interrupt+0x270/0x2bc)
[   64.182309]  r9:ef308000 r8:ef008000 r7:000000a6 r6:c1022048 r5:00000000 r4:ef2ec300
[   64.182322] [<c0282228>] (note_interrupt) from [<c027f6c0>] (handle_irq_event_percpu+0x54/0x60)
[   64.182333]  r10:c02807ac r9:ef308000 r8:ef008000 r7:00000000 r6:c1022048 r5:ef2ec300
[   64.182341]  r4:00000002 r3:00000000
[   64.182353] [<c027f66c>] (handle_irq_event_percpu) from [<c027f70c>] (handle_irq_event+0x40/0x64)
[   64.182361]  r5:ef2ec364 r4:ef2ec300
[   64.182374] [<c027f6cc>] (handle_irq_event) from [<c0283020>] (handle_fasteoi_irq+0xac/0x160)
[   64.182383]  r7:00000000 r6:c1022048 r5:ef2ec364 r4:ef2ec300
[   64.182396] [<c0282f74>] (handle_fasteoi_irq) from [<c027e7f4>] (generic_handle_irq+0x2c/0x3c)
[   64.182405]  r7:00000000 r6:00000000 r5:000000a6 r4:c0e64b3c
[   64.182416] [<c027e7c8>] (generic_handle_irq) from [<c027ed7c>] (__handle_domain_irq+0x64/0xbc)
[   64.182427] [<c027ed18>] (__handle_domain_irq) from [<c0201474>] (gic_handle_irq+0x44/0x80)
[   64.182438]  r9:ef308000 r8:fa213000 r7:fa212000 r6:ef309e98 r5:fa21200c r4:c1004000
[   64.182449] [<c0201430>] (gic_handle_irq) from [<c020c378>] (__irq_svc+0x58/0x8c)
[   64.182457] Exception stack(0xef309e98 to 0xef309ee0)
[   64.182466] 9e80:                                                       ef2ec364 00000800
[   64.182477] 9ea0: ef2ec300 000093e7 ef2ec300 ef2ec364 ef2e9e80 ef2ec314 ef2ec300 ef2e9e80
[   64.182487] 9ec0: c02807ac ef309ef4 ef309ef8 ef309ee8 c02806cc c094a000 20000013 ffffffff
[   64.182497]  r9:ef308000 r8:ef2ec300 r7:ef309ecc r6:ffffffff r5:20000013 r4:c094a000
[   64.182511] [<c0949fd8>] (_raw_spin_unlock_irq) from [<c02806cc>] (irq_finalize_oneshot.part.1+0x84/0xe0)
[   64.182524] [<c0280648>] (irq_finalize_oneshot.part.1) from [<c0280800>] (irq_thread_fn+0x54/0x5c)
[   64.182533]  r7:00000001 r6:00000000 r5:ef2ec300 r4:ef2e9e80
[   64.182546] [<c02807ac>] (irq_thread_fn) from [<c0280ad0>] (irq_thread+0x14c/0x204)
[   64.182554]  r7:00000001 r6:00000000 r5:ffffe000 r4:ef2e9ea4
[   64.182568] [<c0280984>] (irq_thread) from [<c0248ba8>] (kthread+0x164/0x16c)
[   64.182578]  r10:ef07d928 r9:c0280984 r8:ef2e9e80 r7:ef308000 r6:00000000 r5:ef2e9ec0
[   64.182585]  r4:ef2e9f00
[   64.182598] [<c0248a44>] (kthread) from [<c0207d18>] (ret_from_fork+0x14/0x3c)
[   64.182608]  r10:00000000 r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:c0248a44
[   64.182615]  r4:ef2e9ec0
[   64.182622] handlers:
[   64.182631] [<c027f784>] irq_default_primary_handler threaded [<c06716a8>] regmap_irq_thread
[   64.182651] Disabling IRQ #166
[   64.183647] palmas 0-0058: Muxing GPIO 51, PWM 0, LED 2
[   64.185196] SMPS1: supplied by evm_3v3_sd
[   64.186901] SMPS2: supplied by evm_3v3_sd
[   64.188561] SMPS3: supplied by evm_3v3_sd
[   64.190223] SMPS4: supplied by evm_3v3_sd
[   64.191741] SMPS5: supplied by evm_3v3_sd
[   64.192991] SMPS12: supplied by evm_3v3_sd
[   64.194016] LDO1: supplied by evm_3v3_sd
[   64.194533] ldo1: Bringing 3000000uV into 3300000-3300000uV
[   64.203665] LDO2: supplied by evm_3v3_sd
[   64.213403] LDO3: supplied by evm_3v3_sd
[   64.223425] LDO4: supplied by evm_3v3_sd
[   64.233430] LDO5: supplied by evm_3v3_sd
[   64.244582] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
[   64.244764] media: Linux media interface: v0.10
[   64.244803] Linux video capture interface: v2.00
[   64.244886] pps_core: LinuxPPS API ver. 1 registered
[   64.244894] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[   64.244914] PTP clock support registered
[   64.244941] EDAC MC: Ver: 3.0.0
[   64.252886] dmi: Firmware registration failed.
[   64.253101] omap-mailbox: probe of 4883c000.mailbox failed with error -22
[   64.253165] omap-mailbox: probe of 4883e000.mailbox failed with error -22
[   64.253456] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[   64.253557] omap-mailbox: probe of 48842000.mailbox failed with error -22
[   64.253843] Advanced Linux Sound Architecture Driver Initialized.
[   64.262959] clocksource: Switched to clocksource arch_sys_counter
[   64.270554] NET: Registered protocol family 2
[   64.271093] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[   64.271157] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[   64.271284] TCP: Hash tables configured (established 8192 bind 8192)
[   64.271352] UDP hash table entries: 512 (order: 2, 16384 bytes)
[   64.271384] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[   64.271502] NET: Registered protocol family 1
[   64.291856] RPC: Registered named UNIX socket transport module.
[   64.291866] RPC: Registered udp transport module.
[   64.291874] RPC: Registered tcp transport module.
[   64.291881] RPC: Registered tcp NFSv4.1 backchannel transport module.
[   64.292758] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[   64.292888] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
[   64.293933] workingset: timestamp_bits=14 max_order=18 bucket_order=4
[   64.298094] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[   64.308655] NFS: Registering the id_resolver key type
[   64.308678] Key type id_resolver registered
[   64.308687] Key type id_legacy registered
[   64.308724] ntfs: driver 2.1.32 [Flags: R/O].
[   64.310373] bounce: pool size: 64 pages
[   64.310419] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[   64.310430] io scheduler noop registered
[   64.310439] io scheduler deadline registered
[   64.310531] io scheduler cfq registered (default)
[   64.310540] io scheduler mq-deadline registered
[   64.310549] io scheduler kyber registered
[   64.315018] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[   64.315166] pinctrl-single 4a002e8c.pinmux: please update dts to use #pinctrl-cells = <1>
[   64.315239] pinctrl-single 4a002e8c.pinmux: initialized with no interrupts
[   64.315251] pinctrl-single 4a002e8c.pinmux: 1 pins at pa fc002e8c size 4
[   64.330287] vdd_3v3: supplied by ldo1
[   64.330562] aic_dvdd_fixed: supplied by vdd_3v3
[   64.373107] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[   64.375870] 4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 43, base_baud = 3000000) is a 8250
[   65.604768] console [ttyS0] enabled
[   65.609188] 48068000.serial: ttyS5 at MMIO 0x48068000 (irq = 44, base_baud = 3000000) is a 8250
[   65.618815] 48420000.serial: ttyS6 at MMIO 0x48420000 (irq = 45, base_baud = 3000000) is a 8250
[   65.628414] 48422000.serial: ttyS7 at MMIO 0x48422000 (irq = 46, base_baud = 3000000) is a 8250
[   65.638958] omap_rng 48090000.rng: Random Number Generator ver. 20
[   65.646094] DSS: OMAP DSS rev 6.1
[   65.650523] omapdss_dss 58000000.dss: bound 58001000.dispc (ops dispc_component_ops)
[   65.669912] brd: module loaded
[   65.678483] loop: module loaded
[   65.684447] libphy: Fixed MDIO Bus: probed
[   65.742978] davinci_mdio 48485000.mdio: davinci mdio revision 1.6, bus freq 1000000
[   65.750672] davinci_mdio 48485000.mdio: detected phy mask fffffdff
[   65.769471] libphy: 48485000.mdio: probed
[   65.773558] davinci_mdio 48485000.mdio: phy[9]: device 48485000.mdio:09, driver NS DP83848C 10/100 Mbps PHY
[   65.784036] cpsw 48484000.ethernet: No slave[1] phy_id, phy-handle, or fixed-link property
[   65.792361] cpsw 48484000.ethernet: Detected MACID = 5c:f8:21:3d:51:2a
[   65.799040] cpsw 48484000.ethernet: initialized cpsw ale version 1.4
[   65.805463] cpsw 48484000.ethernet: ALE Table size 1024
[   65.810721] cpsw 48484000.ethernet: device node lookup for pps timer failed
[   65.817785] cpsw 48484000.ethernet: cpts: overflow check period 500 (jiffies)
[   65.826211] i2c /dev entries driver
[   65.830401] IR NEC protocol handler initialized
[   65.834978] IR RC5(x/sz) protocol handler initialized
[   65.840050] IR RC6 protocol handler initialized
[   65.844611] IR JVC protocol handler initialized
[   65.849158] IR Sony protocol handler initialized
[   65.853807] IR SANYO protocol handler initialized
[   65.858529] IR Sharp protocol handler initialized
[   65.863478] IR MCE Keyboard/mouse protocol handler initialized
[   65.869335] IR XMP protocol handler initialized
[   65.876006] tmp102 0-0049: initialized
[   65.882229] cpu cpu0: dev_pm_opp_set_regulators: no regulator (vdd) found: -19
[   65.889902] sdhci: Secure Digital Host Controller Interface driver
[   65.896125] sdhci: Copyright(c) Pierre Ossman
[   65.900975] sdhci-pltfm: SDHCI platform and OF driver helper
[   65.907717] ledtrig-cpu: registered to indicate activity on CPUs
[   65.917547] NET: Registered protocol family 10
[   65.932753] Segment Routing with IPv6
[   65.936558] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[   65.942941] NET: Registered protocol family 17
[   65.947648] Key type dns_resolver registered
[   65.952053] omap_voltage_late_init: Voltage driver support not added
[   65.958455] Power Management for TI OMAP4+ devices.
[   65.963608] Registering SWP/SWPB emulation handler
[   65.980833] dmm 4e000000.dmm: workaround for errata i878 in use
[   65.988449] dmm 4e000000.dmm: initialized all PAT entries
[   65.995072] hctosys: unable to open rtc device (rtc0)
[   66.000718] pbias_mmc_omap5: disabling
[   66.004552] ALSA device list:
[   66.007533]   No soundcards found.
[   66.011609] Waiting for root device PARTUUID=23d2adc0-02...
��

Part Number:PROCESSOR-SDK-AM57X

Tool/software: Linux

Hi,

We are using PROCESSOR-SDK-AM57X ti-processor-sdk-linux-am57xx-evm-05.02.00.10, using UART1 (ttyO0) and customized am571x-idk. Board.c and mux-data.h is modified as per am571x-idk. Booting through sd card by creating bootable sd card using this(tisdk-rootfs-image-am57xx-evm.tar.xz) tarball.   

Uboot log in is coming and showing that no pinctrl state for default mode. please find the below attached log and Uboot prompt.

Kindly suggest what's wrong.

U-BOOT PROMPT

U-Boot SPL 2018.01-00558-gca1e85ecb5-dirty (Jan 12 2019 - 14:56:01)
DRA722-GP ES1.0
Trying to boot from MMC1
no pinctrl state for default mode
no pinctrl state for default mode


U-Boot 2018.01-00558-gca1e85ecb5-dirty (Jan 12 2019 - 14:56:01 +0530)

CPU  : DRA722-GP ES1.0
Model: TI AM5718 IDK
Board: AM571x IDRAM:  1 GiB
MMC:   prop_name: pinctrl-0 mode: default index: 0
prop_name: pinctrl-6 mode: sdr104 index: 6
prop_name: pinctrl-4 mode: sdr50 index: 4
prop_name: pinctrl-5 mode: ddr50 index: 5
prop_name: pinctrl-3 mode: sdr25 index: 3
prop_name: pinctrl-2 mode: sdr12 index: 2
prop_name: pinctrl-1 mode: hs index: 1
prop_name: pinctrl-0 mode: default index: 0
prop_name: pinctrl-2 mode: ddr_1_8v index: 2
prop_name: pinctrl-1 mode: hs index: 1
OMAP SD/MMC: 0, OMAP SD/MMC: 1
Warning: fastboot.board_rev: unknown board revision
GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645
part_get_info_efi: *** ERROR: Invalid GPT ***
GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645
part_get_info_efi: *** ERROR: Invalid Backup GPT ***
SCSI:  SATA link 0 timeout.
AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst
scanning bus for devices...
Found 0 device(s).
Net:   Could not get PHY for ethernet@48484000: addr 0

Warning: ethernet@48484000 using MAC address from ROM
eth0: ethernet@48484000
Hit any key to stop autoboot:  0
=>
=>
=>
=> mmc info
Device: OMAP SD/MMC
Manufacturer ID: 2
OEM: 544d
Name: SA08G
Bus Speed: 48000000
Mode : SD High Speed (50MHz)
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 7.2 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
=> mmc
mmc - MMC sub system

Usage:
mmc info - display info of the current MMC device
mmc read addr blk# cnt
mmc write addr blk# cnt
mmc erase blk# cnt
mmc rescan
mmc part - lists available partition on current mmc device
mmc dev [dev] [part] - show or set current mmc device [partition]
mmc list - lists available devices
mmc hwpartition [args...] - does hardware partitioning
  arguments (sizes in 512-byte blocks):
    [user [enh start cnt] [wrrel {on|off}]] - sets user data area attributes
    [gp1|gp2|gp3|gp4 cnt [enh] [wrrel {on|off}]] - general purpose partition
    [check|set|complete] - mode, complete set partitioning completed
  WARNING: Partitioning is a write-once setting once it is set to complete.
  Power cycling is required to initialize partitions after set to complete.
mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode
 - Set the BOOT_BUS_WIDTH field of the specified device
mmc bootpart-resize <dev> <boot part size MB> <RPMB part size MB>
 - Change sizes of boot and RPMB partitions of specified device
mmc partconf dev [boot_ack boot_partition partition_access]
 - Show or change the bits of the PARTITION_CONFIG field of the specified device
mmc rst-function dev value
 - Change the RST_n_FUNCTION field of the specified device
   WARNING: This is a write-once field and 0 / 1 / 2 are the only valid values.
mmc setdsr <value> - set DSR register value

=> mmc part

Partition Map for MMC device 0  --   Partition Type: DOS

Part    Start Sector    Num Sectors     UUID            Type
  1     2048            143360          23d2adc0-01     0c Boot
  2     145408          14952448        23d2adc0-02     83
=> ������

Part Number:AM3358

The PRU_Demo in the support package contains the following snippets  in pru.c

1)

//******************************************************************************
//    PRU ICSS Reset
//      This function resets the PRU cores.
//******************************************************************************
void PRUICSSReset(void)
{

    HWREG(SOC_PRM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) |= 0x2;    /* Reset PRU */  // should be: RM_PER_RSTCTRL
    HWREG(SOC_PRM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &= 0xFFFFFFFD;

}

Question 1: I would think that the offset should rather be RM_PER_RSTCTRL (refman AM335x  p.1411), since this is related to the PER domain resets, not to clock management.

Since the value of CM_PER_L4LS_CLKSTCTRL is the same as RM_PER_RSTCTRL,namely 0, the difference has no impact.

2)

//******************************************************************************
//    PRU Memory Fill
//      This function takes and a pointer length and value to be placed and
//      iterates through the memory placing the pattern.
//******************************************************************************
void PRUMemFill(unsigned int StartAddress, unsigned int Length, unsigned int  Pattern)
{

    memset((unsigned char*)StartAddress, Pattern, (Length/4));

}

Question 2: why is the nb of bytes to be filled divided by 4 ?.

Thanks

Peter

Part Number:PRUCAPE

The mentioned document states (table 1) that:

MCASP0_FSX is connected to  PRU0 Orange LED

MCASP0_AXR0 is connected to PRU0 Green Led

Based on my tests, these are swapped, that is MCASP0_FSX => Green and MCASP0_AXR0 => Orange

Thanks

Peter