Hi,

I'm trying to figure out the timing delay between the trigger's rising edge and the the first instruction of its ISR function on AM1806. The porgram is simple:

main() : Initialization followed by while(1)

FIQ ISR: Tirggered by an external signal's Rising edge （once per second ) and Pull Up and Pull Down a GPIO Output Signal.

I observed the Rising Edge of the Trigger and the Gpio Output Signal and found that the timing delay between them was changing every time. The difference might be larger than 1us.

I want to know whether the timing delay between the trigger and the ISR is a CONSTANT value or a VOLATILE value?

Thank you!

Hi,

In the following document:

"www.ti.com/.../omap-l138.pdf"

In section 6.16 it states:

'If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater.'

What is the consequence if a value of zero is used? I've tried it set to zero and it appears to work.

Not being able to set it to zero does limit the max speed that can be used especially when running at 1.0V (PLL_SYSCLK2 max is 75MHz, if CLKGDV has to be 1 or more this means max McBSP rate is 37.5MHz).

Thanks

Nigel

Hi.

We are working on OMAP-L138 custom board. We have some problems with all the NAND commands from u-boot.

The nand seems to be correctly identified. but reads and dumps fails with error, write don't seem to be properly:

We are using latest mcsdk_1_01_00_02

Here is my memory contents after fatload command:

U-Boot > md 0xc0700000
c0700000: 56190527 5799701b 62516d56 9f732900    '..V.p.WVmQb.)s.
c0700010: 008000c0 008000c0 ff86a335 00020205    ........5.......
c0700020: 756e696c 2e332d78 332e3431 00354237    linux-3.14.37B5.
c0700030: 00000000 00000000 00000000 00000000    ................
c0700040: e1a00000 e1a00000 e1a00000 e1a00000    ................
c0700050: e1a00000 e1a00000 e1a00000 e1a00000    ................
c0700060: ea000002 016f2818 00000000 00295888    .....(o......X).
c0700070: e10f9000 e1a07001 e1a08002 e10f2000    .....p....... ..
c0700080: e3120003 1a000001 e3a00017 ef123456    ............V4..
c0700090: e321f0d3 e16ff009 00000000 00000000    ..!...o.........
c07000a0: e59f47d8 e1a0000f e1500004 359f0164    .G........P.d..5
c07000b0: 3080000f 31540000 33844001 2b000057    ...0..T1.@.3W..+
c07000c0: e28f0e13 e8901c4e e590d01c e0400001    ....N.........@.
c07000d0: e0866000 e08aa000 e5da9000 e5dae001    .`..............
c07000e0: e189940e e5dae002 e5daa003 e189980e    ................
c07000f0: e1899c0a e08dd000 e28da801 e3a05000    .............P..

When i issue 'nand erase 0x20000 0x80000' then 'nand write.trimffs 0xc0700000 0x20000 0x80000' i get '524288 bytes written OK'

Then when i issue 'nand dump 0x20000' i get:

nand dump 0x20000
Page 00020000 dump:
        27 ff 19 ff 1b ff 99 ff  56 ff 51 ff 00 ff 73 ff
        c0 ff 80 ff c0 ff 80 ff  35 ff 86 ff 05 ff 02 ff
        6c ff 6e ff 78 ff 33 ff  31 ff 2e ff 37 ff 35 ff
        00 ff 00 ff 00 ff 00 ff  00 ff 00 ff 00 ff 00 ff
        00 ff a0 ff 00 ff a0 ff  00 ff a0 ff 00 ff a0 ff
        00 ff a0 ff 00 ff a0 ff  00 ff a0 ff 00 ff a0 ff
        02 ff 00 ff 18 ff 6f ff  00 ff 00 ff 88 ff 29 ff
        00 ff 0f ff 01 ff a0 ff  02 ff a0 ff 00 ff 0f ff
        03 ff 12 ff 01 ff 00 ff  17 ff a0 ff 56 ff 12 ff
        d3 ff 21 ff 09 ff 6f ff  00 ff 00 ff 00 ff 00 ff
        d8 ff 9f ff 0f ff a0 ff  04 ff 50 ff 64 ff 9f ff
        0f ff 80 ff 00 ff 54 ff  01 ff 84 ff 57 ff 00 ff
        13 ff 8f ff 4e ff 90 ff  1c ff 90 ff 01 ff 40 ff
        00 ff 86 ff 00 ff 8a ff  00 ff da ff 01 ff da ff
        0e ff 89 ff 02 ff da ff  03 ff da ff 0e ff 89 ff
        0a ff 89 ff 00 ff 8d ff  01 ff 8d ff 00 ff a0 ff
        01 ff 8a ff 0a ff 54 ff  16 ff 00 ff 09 ff 84 ff
        50 ff 8f ff 09 ff 5a ff  12 ff 00 ff 02 ff 8a ff
        ff ff ca ff 6c ff 4f ff  1f ff c5 ff 05 ff 46 ff
        1f ff 89 ff 1f ff c9 ff  05 ff 89 ff 0a ff 89 ff
        0f ff 36 ff 05 ff 56 ff  0f ff 29 ff fb ff ff ff
        06 ff 49 ff 06 ff 8d ff  50 ff 00 ff a4 ff 4f ff
        06 ff 80 ff 00 ff a0 ff  05 ff 90 ff 0d ff 00 ff
        00 ff 8b ff 00 ff 8c ff  00 ff 82 ff 00 ff 83 ff
        00 ff 9b ff 00 ff 81 ff  02 ff 51 ff 01 ff 53 ff
        05 ff 81 ff 04 ff 8b ff  0c ff 5b ff f7 ff ff ff
        05 ff 82 ff 05 ff 83 ff  00 ff a0 ff 04 ff 82 ff
        04 ff 82 ff 04 ff 82 ff  04 ff 82 ff 03 ff 52 ff
        f9 ff ff ff 01 ff 14 ff  01 ff c4 ff 13 ff 00 ff
        04 ff a0 ff 0d ff a0 ff  01 ff 8d ff 07 ff a0 ff
        0b ff 00 ff 2d ff 00 ff  04 ff 00 ff 07 ff a0 ff
        08 ff a0 ff a4 ff 00 ff  b8 ff 00 ff 88 ff 29 ff
        a8 ff 29 ff 88 ff 29 ff  43 ff 29 ff 54 ff 29 ff
        80 ff 29 ff a8 ff 29 ff  28 ff 39 ff 00 ff 20 ff
        08 ff a0 ff 88 ff 00 ff  3f ff a0 ff 17 ff 06 ff
        37 ff 06 ff 80 ff a0 ff  10 ff 02 ff 30 ff 02 ff
        10 ff 03 ff 03 ff a0 ff  30 ff 05 ff 10 ff 05 ff
        00 ff a0 ff 9a ff 07 ff  15 ff 07 ff 16 ff 07 ff
        10 ff 11 ff 2d ff 80 ff  01 ff 80 ff 10 ff 01 ff
        00 ff a0 ff 15 ff 07 ff  16 ff 07 ff 0e ff a0 ff
        3f ff a0 ff 17 ff 06 ff  80 ff a0 ff 10 ff 02 ff
        10 ff 03 ff 03 ff a0 ff  10 ff 05 ff 00 ff a0 ff
        10 ff 07 ff 10 ff 11 ff  0d ff 80 ff 00 ff a0 ff
        10 ff 01 ff 10 ff 07 ff  0e ff a0 ff 01 ff 44 ff
        ff ff c3 ff 3f ff c3 ff  03 ff a0 ff 20 ff a0 ff
        09 ff a0 ff 01 ff 89 ff  12 ff a0 ff 03 ff 81 ff
        01 ff 83 ff 09 ff 51 ff  01 ff 5a ff 1c ff c1 ff
        10 ff 81 ff 06 ff 81 ff  04 ff 80 ff 01 ff 81 ff
        02 ff 30 ff f6 ff ff ff  04 ff 86 ff 03 ff 81 ff
        0f ff a0 ff 22 ff a0 ff  02 ff 81 ff 02 ff 83 ff
        04 ff 80 ff 01 ff 81 ff  00 ff 80 ff 0e ff a0 ff
        10 ff 11 ff 02 ff c0 ff  01 ff 80 ff 10 ff 01 ff
        01 ff 00 ff 04 ff a0 ff  10 ff ef ff 0e ff a0 ff
        1a ff a0 ff d8 ff ff ff  00 ff a0 ff 9a ff 07 ff
        17 ff 08 ff 10 ff 11 ff  05 ff 80 ff 30 ff 80 ff
        2c ff 00 ff 00 ff a0 ff  17 ff 08 ff 0c ff a0 ff
        0e ff a0 ff 91 ff 10 ff  0f ff 1b ff 0a ff a0 ff
        c9 ff ff ff 00 ff a0 ff  9a ff 07 ff 0f ff 1b ff
        17 ff 08 ff 10 ff 11 ff  01 ff c0 ff 05 ff 80 ff
        3c ff 80 ff 02 ff c0 ff  01 ff 80 ff 50 ff 12 ff
        01 ff 80 ff 02 ff e0 ff  02 ff c6 ff 03 ff c6 ff
        10 ff 02 ff 10 ff 03 ff  50 ff 02 ff 95 ff 07 ff
        10 ff 01 ff 10 ff 11 ff  00 ff a0 ff 95 ff 07 ff
        0c ff a0 ff 0e ff a0 ff  1a ff a0 ff ae ff ff ff
        00 ff a0 ff 17 ff 07 ff  9a ff 07 ff 17 ff 08 ff
        10 ff 11 ff 01 ff 80 ff  02 ff 00 ff 00 ff a0 ff
        17 ff 08 ff 0c ff a0 ff  0d ff 80 ff 00 ff e0 ff
        10 ff 02 ff 10 ff 03 ff  00 ff 00 ff 00 ff 20 ff
        10 ff 01 ff 10 ff 11 ff  20 ff 4e ff 1c ff 8f ff
        10 ff 10 ff 00 ff 9c ff  04 ff 9c ff 09 ff 21 ff
        02 ff 11 ff 03 ff 8c ff  14 ff 8c ff f8 ff ff ff
        00 ff 00 ff 00 ff 00 ff  0e ff a0 ff 0e ff a0 ff
        0e ff a0 ff 00 ff 00 ff  00 ff f8 ff 0e ff a0 ff
        0e ff a0 ff 0e ff a0 ff  00 ff 80 ff 00 ff ff ff
        a9 ff ff ff 65 ff 00 ff  0e ff a0 ff 00 ff 00 ff
        00 ff 00 ff 71 ff ff ff  5a ff 00 ff ea ff 00 ff
        00 ff 00 ff 00 ff 00 ff  56 ff ff ff 4d ff 00 ff
        74 ff 00 ff 60 ff 06 ff  f0 ff 0f ff 98 ff ff ff
        56 ff 00 ff be ff 00 ff  00 ff 00 ff 00 ff 00 ff
        0e ff a0 ff 0e ff a0 ff  0e ff a0 ff 00 ff 01 ff
        e0 ff ff ff 90 ff ff ff  4c ff 00 ff bb ff 00 ff
        10 ff 01 ff f0 ff ff ff  8b ff ff ff 47 ff 00 ff
        b6 ff 00 ff 00 ff 05 ff  00 ff ff ff 86 ff ff ff
        42 ff 00 ff b1 ff 00 ff  00 ff 15 ff 00 ff ff ff
        81 ff ff ff 3d ff 00 ff  a5 ff 00 ff 00 ff 05 ff
        00 ff 0f ff 7c ff ff ff  38 ff 00 ff a0 ff 00 ff
        61 ff 01 ff f1 ff 01 ff  a1 ff ff ff 33 ff 00 ff
        5c ff 00 ff 00 ff 02 ff  00 ff 0f ff 72 ff ff ff
        2e ff 00 ff 9d ff 00 ff  00 ff 05 ff 00 ff 0f ff
        6d ff ff ff 29 ff 00 ff  98 ff 00 ff 00 ff 06 ff
        00 ff 0f ff 68 ff ff ff  24 ff 00 ff 8c ff 00 ff
        00 ff 07 ff 00 ff 0f ff  5c ff ff ff 1f ff 00 ff
        4f ff 00 ff 00 ff 0f ff  00 ff 0f ff 6b ff ff ff
        21 ff 00 ff 51 ff 00 ff  00 ff 00 ff 00 ff 00 ff
        0e ff a0 ff 0e ff a0 ff  0e ff a0 ff 00 ff 20 ff
        00 ff 20 ff 00 ff 20 ff  00 ff 20 ff 00 ff 20 ff
        0c ff a0 ff 90 ff ff ff  10 ff 11 ff 0d ff c0 ff
        10 ff 01 ff 00 ff a0 ff  9a ff 07 ff 16 ff 07 ff
        15 ff 07 ff 0e ff a0 ff  10 ff 11 ff 0d ff c0 ff
        10 ff 01 ff 00 ff a0 ff  10 ff 07 ff 0e ff a0 ff
        10 ff 11 ff 0d ff c0 ff  10 ff 01 ff 00 ff a0 ff
        17 ff 07 ff 17 ff 08 ff  0e ff a0 ff 10 ff 11 ff
        0d ff c0 ff 10 ff 01 ff  0e ff a0 ff 2b ff 00 ff
        00 ff a0 ff 17 ff 08 ff  d5 ff 07 ff 9a ff 07 ff
        95 ff 07 ff 0c ff a0 ff  00 ff 20 ff 00 ff 20 ff
        00 ff 20 ff 00 ff 20 ff  00 ff 20 ff 00 ff 20 ff
        10 ff a0 ff 68 ff ff ff  01 ff 14 ff 0e ff a0 ff
        01 ff a0 ff 00 ff a0 ff  16 ff 07 ff e0 ff a0 ff
        3f ff 81 ff 5e ff 07 ff  01 ff 53 ff fc ff ff ff
        20 ff 51 ff f9 ff ff ff  00 ff 32 ff 15 ff 07 ff
        9a ff 07 ff 0e ff a0 ff  01 ff 14 ff 0e ff a0 ff
        00 ff a0 ff 1e ff 07 ff  15 ff 07 ff 9a ff 07 ff
        0e ff a0 ff 00 ff a0 ff  01 ff 14 ff 1e ff 07 ff
        15 ff 07 ff 1f ff 07 ff  9a ff 07 ff 0e ff a0 ff
        01 ff 14 ff 29 ff 00 ff  b1 ff 10 ff 0f ff 1a ff
        00 ff a0 ff 01 ff 00 ff  1e ff 07 ff 23 ff 00 ff
        ba ff 07 ff ff ff 2d ff  30 ff 30 ff 07 ff 10 ff
        a3 ff a0 ff 1a ff 00 ff  00 ff a0 ff aa ff 8a ff
        30 ff a0 ff 07 ff 01 ff  02 ff 51 ff 11 ff 00 ff
        10 ff 40 ff 95 ff 07 ff  10 ff 30 ff 07 ff 01 ff
        04 ff 82 ff f8 ff 9f ff  a1 ff 14 ff 14 ff 6f ff
        f0 ff 9f ff a1 ff 17 ff  04 ff a0 ff 19 ff 8a ff
        17 ff 8b ff 5e ff 07 ff  01 ff 59 ff fa ff ff ff
        01 ff 57 ff f7 ff ff ff  02 ff 8a ff 0a ff 53 ff
        e5 ff ff ff ff ff bd ff  00 ff a0 ff 10 ff 40 ff
        9a ff 07 ff 15 ff 07 ff  9a ff 07 ff 95 ff 07 ff
        0e ff a0 ff 01 ff 14 ff  0e ff a0 ff 7e ff 17 ff
        fd ff ff ff 15 ff 07 ff  9a ff 07 ff 0e ff a0 ff
OOB:
        ff ff ff ff ff ff ff ff
        ff ff ff ff ff ff ff ff
        ff ff ff ff ff ff ff ff
        ff ff ff ff ff ff ff ff
        ff ff ff ff ff ff ff ff
        f3 ff f3 ff a6 ff 99 ff
        ab ff 5a ff aa ff 5b ff
        c0 ff 99 ff 67 ff 96 ff
Command failed, result=1

when i issue 'nand read 0xc0700000 0x20000 0x80000' i get:

NAND read: device 0 offset 0x20000, size 0x80000
NAND read from offset 20000 failed -74
 0 bytes read: ERROR

My UBOOT configuration for nand is:

#ifdef CONFIG_USE_NAND
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_ENV_IS_IN_NAND            /* U-Boot env in NAND Flash  */
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_OVERWRITE
//#define CFG_DAVINCI_STD_NAND_LAYOUT
#define CONFIG_CMD_NAND_TRIMFFS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS

#define CONFIG_MTDDEBUG 

#define CONFIG_ENV_OFFSET               0x0 /* Block 0--not used by bootcode */
#define CONFIG_ENV_SIZE                 (128 << 9)
#define CONFIG_MTD_DEVICE
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#undef CONFIG_SYS_NAND_BUSWIDTH_16_BIT
#define CONFIG_SYS_NAND_CS              2
#define CONFIG_SYS_NAND_BASE            DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
#define CONFIG_SYS_CLE_MASK             0x10
#define CONFIG_SYS_ALE_MASK             0x8
#undef CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE      1 /* Max number of NAND devices */
#define NAND_MAX_CHIPS                  1
#endif

What could be the cause for this fault? 

Kind Regards

I am facing the following problem on the LCDK kit for OMAP L138:

I have 4 no. of LCDK kits. Only on one kit CODEC loopback is working. The file I am using for testing comes with the STARTERWARE for OMAP l138 in the foder titled "binary " containing the .out files generated for testing purposes. The mcasp example is being used for loopback of line_in to line_out.If some hardware problem is  there in the dac path or adc path where to look at and how to debug .Please provide suggestions...

Thanks and Regards

KAUSHAL KUMAR

As I saw in the SYS/BIOS config file my DSP runs on 300 MHz.

I wanna change the clock frequency to 48 MHz. How should I do that? Is it an only way to make a platform files manually, or should I write to the appropriate clock registers myself? I run my DSP code separately from ARM, ARM works without Linux (actually I just load uBoot from the FLASH which starts DDR and ARM cores).

Hi TI Experts,

Please let me confirm the following question.

[Question]
Do you have a NAND Flash Controller software for C674x EMIF interface?
It means that C674x controls the bad block or Reclamation for NAND.

If you have any questions, please let me know.
Best regards.
Kaka

Hi,

I have a question about OMAPL138 PLL initializaiton procedure.

I refer to device_PLL0() in EVMOMAPL138_ARM.gel included in CCSv6.
In device_PLL0(), there are the following code.

   /* Set PLLEN=0 to put in bypass mode*/
   PLL0_PLLCTL &= ~(0x00000001);

   /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
   for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

   ....

   /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
   for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

Is this waiting time(PLL stabilisation time) necessary in here?
If comment is correct, I think that it is not necessary, because PLL is in bypass mode already at that point.

I checked OMAPL138 Technical Reference Manual and datasheet, but was not able to find the description about it.
Please tell me whether waiting time(PLL stabilisation time) is necessary or not, in OMAPL138 PLL initialization procedure.

Best Regards,
Yasunori

Dear Team,

Is there any method to attach SATA3 SSD on SATA port of OMAP-L138 stably?

If external PMP device used, does this help to stable connection with SATA3 SSD?

As you know, it is hard to find out SATA2 SSD anymore as SATA3 SSD is getting popular, and my customer need to connect SSD.

So, they want to check if there is any method to connect SATA3 SSD stably even when external device like PMP was used.

Could you please check this and let me know what is most stable method to connect SATA3 SSD?

Thanks and Best Regards,

SI.

 JFFS2 notice: (1142) jffs2_get_inode_nodes
: Node header CRC failed at 0x0aea40. {ffff,ffff,ffffffff,ffffffff}
mtd->read(0x60 bytes from 0xa3fa0) returned ECC error
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0x0a3fa0.
{0000,0000,48000000,85fda645}
JFFS2 warning: (1142) jffs2_do_read_inode_internal: no data nodes found for ino
#790
JFFS2 notice: (1142) jffs2_do_read_inode_internal: but it has children so we fak
e some modes for it
device eth0 left promiscuous mode
JFFS2 warning: (1411) jffs2_sum_write_data: Not enough space for summary, padsiz
e = -218
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0x0e99c8.
{ffff,ffff,ffffffff,ffffffff}
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0x0e9844.
{ffff,ffff,ffffffff,ffffffff}
mtd->read(0x574 bytes from 0xe8a8c) returned ECC error
mtd->read(0x4d4 bytes from 0x122b2c) returned ECC error
mtd->read(0xe8b bytes from 0x14f000) returned ECC error
mtd->read(0x7a0 bytes from 0x13c000) returned ECC error
mtd->read(0x52e bytes from 0x123800) returned ECC error
mtd->read(0x4a6 bytes from 0x160800) returned ECC error
JFFS2 notice: (1142) check_node_data: wrong data CRC in data node at 0x00160250:
 read 0xdde13e86, calculated 0x3eef42e5.
mtd->read(0x569 bytes from 0x202800) returned ECC error
mtd->read(0x298 bytes from 0x200800) returned ECC error
mtd->read(0x4de bytes from 0x1b4800) returned ECC error
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0x2e255c.
{ffff,ffff,ffffffff,ffffffff}
mtd->read(0x34 bytes from 0x27bfcc) returned ECC error
JFFS2 notice: (1142) read_dnode: node CRC failed on dnode at 0x27bfcc: read 0x66
fec2af, calculated 0xc38e1c0d
mtd->read(0x7fc bytes from 0x29f800) returned ECC error
mtd->read(0x9dd bytes from 0x242800) returned ECC error
JFFS2 notice: (1142) check_node_data: wrong data CRC in data node at 0x00242720:
 read 0x92e8e325, calculated 0x5005eae5.
mtd->read(0x44 bytes from 0x4d36f0) returned ECC error
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0x4d3da0.
{36a6,b01f,ba4f452e,1de70ac9}
JFFS2 warning: (1142) jffs2_do_read_inode_internal: no data nodes found for ino
#1747
Returned error for crccheck of ino #1747. Expect badness...
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0x4d3e1c.
{3c93,5b6e,05bfdf45,05fe6ea0}
JFFS2 warning: (1142) jffs2_do_read_inode_internal: no data nodes found for ino
#1748
Returned error for crccheck of ino #1748. Expect badness...
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0x4d3e98.
{a86a,4f2c,d0dcf4de,3feaaad3}
JFFS2 warning: (1142) jffs2_do_read_inode_internal: no data nodes found for ino
#1749
Returned error for crccheck of ino #1749. Expect badness...
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0x4d3f14.
{126f,526e,526e126f,00000000}
JFFS2 warning: (1142) jffs2_do_read_inode_internal: no data nodes found for ino
#1750
Returned error for crccheck of ino #1750. Expect badness...
mtd->read(0x73c bytes from 0x4de8c4) returned ECC error
mtd->read(0x16c bytes from 0x4ef694) returned ECC error
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0x540e24.
{ffff,ffff,ffffffff,ffffffff}
mtd->read(0x454 bytes from 0x603bac) returned ECC error
mtd->read(0x271 bytes from 0x5f0000) returned ECC error
JFFS2 notice: (1142) check_node_data: wrong data CRC in data node at 0x005e801c:
 read 0x5a880953, calculated 0xa9b340b.
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0xf50594.
{ffff,ffff,ffffffff,ffffffff}
mtd->read(0x6b4 bytes from 0x14a214c) returned ECC error
mtd->read(0x68d bytes from 0x149f000) returned ECC error
JFFS2 notice: (1142) check_node_data: wrong data CRC in data node at 0x0149ecf8:
 read 0xd1af43b, calculated 0xe29f60b5.
mtd->read(0x4ee bytes from 0x14a5800) returned ECC error
mtd->read(0x44 bytes from 0x14a5cf0) returned ECC error
mtd->read(0x61c bytes from 0x150b9e4) returned ECC error
mtd->read(0x36c bytes from 0x1510494) returned ECC error
mtd->read(0x758 bytes from 0x1526800) returned ECC error
mtd->read(0x1b8 bytes from 0x1552648) returned ECC error
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0x1572130.
 {ffff,ffff,ffffffff,ffffffff}
mtd->read(0x3f8 bytes from 0x1614408) returned ECC error
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0x1614408.
 {bece,facf,81dd8c43,bc43a06f}
mtd->read(0x5c4 bytes from 0x1613a3c) returned ECC error
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0x16118e0.
 {ffff,ffff,ffffffff,ffffffff}
JFFS2 notice: (1142) jffs2_get_inode_nodes: Node header CRC failed at 0x1604a20.
 {ffff,ffff,ffffffff,ffffffff}
mtd->read(0x791 bytes from 0x1621800) returned ECC error

I use the TMDSLCDK board, the OMAP-L138 processor, CCS 6.0.1, SYS/BIOS bios_6_42_03_35 and try to use the edma3_lld_02_11_09_08 driver from MCSDK on the DSP core. But if i try to run examples from LLD package my code crashed at the point:

*hSem = (EDMA3_OS_Sem_Handle)Semaphore_create(initVal, semParams, NULL);

from the function EDMA3_DRV_Result edma3OsSemCreate(int initVal, const Semaphore_Params *semParams, EDMA3_OS_Sem_Handle *hSem).

As I undestand the LLD driver uses a dynamic creation of OS objects, but my project uses static type only. Is it a cause for the crash? If yes, where can I get the LLD driver which uses static OS objects?

Could I get a copy of the C6748 LC DEV KIT VER A7E.DSN that works with Orcad V9.2.

Hi,

I used in our last project Micron PC28F00AP30EFA Nor Flash ,in GPMC interface and it works successful. In our new project we use a new Micron Product that is MT28GU01GAAA2EGC-0AAT. We can read- write to Nor Flash by GPMC Interface but we can not boot in XIP mode from Nor Flash. Sys boot switch is correct for XIP mode i think. Is there any configuration needed in GPMC or ROM code ?

Thank You.

The EVM examples do not use the ARM compiler interrupt keyword, they are simply declared as below:

static void TimerIsr(void)

void edma3CCComplIsr()

How are register values etc. preserved?

I have added the interrupt keyword to one of my interrupt functions which calls another function and the code now crashes. Can someone please explain the correct usage.

I try to switch ARM core wich works with SYS/BIOS into the privileged mode by instruction:

_call_swi(ARM_PRIV_MODE_KEY);

but it leads to falling into an exception handler. The problem is that there is an address of the subroutine of exception situated in the appropriate vector of SWI #0x50000. Why do it situated there? How to switch ARM core into the the privileged mode?

There are some screenshots which can help to understand the problem:

Hi,

I would like to develop an application to play (decode in real-time) MP3 files using a C674x DSP. This would require an MP3 decoder, which is available for C674x here:

Before I spend time trying to set this up, I want to ask if it is possible to use this decoder to stream MP3 files and not just decode an MP3 file to a PCM file. I would like to stream MP3 files, so decoding PCM samples and outputting via McASP on-the-fly. Is this possible using this example MP3 decoder?

Thanks

Brian

All:

OMAPL138, CCS 6.1.1

Has anyone used Debug Server Scripting to do testing of internal memory on a TI processor?

I am specifically interested in memory testing of OMAPL138, but I wanted to check on any processor...

What I would like to do:

1. Write a pattern of 1's and 0's to memory (like 5555... or AAAA...) and read it back to verify.

2. Write a unique pattern to memory and read it back - like write the address of the location as data.

Hi

Are there examples on how to configure mega module to map DSP GPIO Bank 3 interrupt to CPU. I would like to use it as an interrupt event for EDMA3.

We are using lwIP with Starterware on an OMAPL138  and whenever the message data size is greater than an integer number of segments (n x 1460 bytes) + 1 to 4 bytes the data that is sent in the last small segment of 1to 4 bytes is corrupted. So for example 1460 bytes are sent OK, 1461 are not, 1465 are OK. This has been confirmed using Wireshark.

lwipopts.h is as below:

/*****************************************************************************

** lwIP SPECIFIC DEFINITIONS - To be used by lwIP stack

*****************************************************************************/

#define HOST_TMR_INTERVAL 0

#define DYNAMIC_HTTP_HEADERS

/*****************************************************************************

** Platform specific locking

*****************************************************************************/

#define SYS_LIGHTWEIGHT_PROT 1

#define NO_SYS 1

/*****************************************************************************

** Memory Options

*****************************************************************************/

#define MEM_ALIGNMENT 4

//#define MEM_SIZE (30 * 1024) /* 30K */

#define MEM_SIZE (60 * 1024) /* 30K */

/*****************************************************************************

** Memory Options

*****************************************************************************/

#define MEMP_NUM_PBUF 48

#define MEMP_NUM_TCP_PCB 16

#define PBUF_POOL_SIZE 96

/*****************************************************************************

** Memory Options

*****************************************************************************/

#define IP_REASSEMBLY 0

#define IP_FRAG 0

/*****************************************************************************

** DHCP Options

*****************************************************************************/

#define LWIP_DHCP 1

#define DHCP_DOES_ARP_CHECK 0

/*****************************************************************************

** Auto IP Options

*****************************************************************************/

#define LWIP_AUTOIP 0 /* default is 0 */

#define LWIP_DHCP_AUTOIP_COOP ((LWIP_DHCP) && (LWIP_AUTOIP))

/* default is 0 */

#define LWIP_DHCP_AUTOIP_COOP_TRIES 5 /* default is 9 */

/*****************************************************************************

** TCP Options

*****************************************************************************/

#define TCP_MSS 1500 /* default is 128 */

//#define TCP_WND (8 * TCP_MSS) /* default is 2048 */

//#define TCP_SND_BUF (8 * TCP_MSS)

#define TCP_WND (16 * TCP_MSS) /* default is 2048 */

#define TCP_SND_BUF (16 * TCP_MSS)

/*****************************************************************************

** PBUF Options

*****************************************************************************/

#define PBUF_LINK_HLEN 14 /* default is 14 */

//#define PBUF_POOL_BUFSIZE 256

#define PBUF_POOL_BUFSIZE 1554

/* default is LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN)*/

#define ETH_PAD_SIZE 0

#define LWIP_NETCONN 0 /*default is 1*/

/*****************************************************************************

** Socket Options

*****************************************************************************/

#define LWIP_SOCKET 0 /* default is 1 */

/*****************************************************************************

** Debugging options

*****************************************************************************/

#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_OFF

#define LWIP_DBG_TYPES_ON (LWIP_DBG_ON|LWIP_DBG_TRACE|LWIP_DBG_STATE|LWIP_DBG_FRESH)

/*****************************************************************************

** Checksum options

*****************************************************************************/

//#define CHECKSUM_GEN_TCP 0 // h/w should be able to do this

//#define CHECKSUM_CHECK_IP 0

//#define MEM_USE_POOLS 1

//#define MEMP_USE_CUSTOM_POOLS 1

Dear TI

I am looking for a evaluation board with TI processor , booting from Nandflash or any storage device but no SD card booting, usb,Lan connectivity

the evaluation hardware must be quite cheap like 100 $ or in similar range

Os can be any linux OS either android, ubuntu or any linux flavour

Regards

nick

We have a OMAP-L138 on a custom board with a custom file system - the application we write is in a seperate file system (to remove the change of corruptions etc) ;

Currently we can run c6accell programs with the existing core as supplied.

If we want to add our own functions to the c6acell we need to follow the steps in the advanced feature guide - before i do that, can I ask 

a) is the library static or dynamically linked

b) when the document says - the codec server is consumed by the application" - what does that mean ?

"The rebuild compiles the source files and archives the C6accel library files in the
$(C6ACCEL_INSTALL_DIR)/soc/paclages/ti/c6acel/lib to be consumed by the application. When the codec server
builds , it picks up this library, therby integrating the new kernel in the DSP executable that gets consumed in the
application."

So is all new functionality included in the final app or does it need additional "dynamic" resources ?

b