Recently, we are working on a product enhancement project, the DSP processor is TMS320VC33, during debugging, we have found an issue.
We use a DMA interrupt to copy data from the serial port 0 of the DSP to implement analogue signal sampling. The DMA count is set to 16, the DMA source address is set to Serial port 0 receive address, and the DMA destination address is set to a INT32 array with length 16.
The serial port 0 received data length is 16bits.
This setting means that in every analogue sample, there are 16 channels, the data length of every channel is 16bits. Everytime, the serial port has received a 16bits data, DMA-coprocessor will move the data to array[0]. Serial port receiving the data of 2nd channel, and then DMA-coprocessor move it to the array[1], and so on.
We use two boards, one is responsible for analogue sampling and another is responsible for other calculation. The two boards use a sharedRAM to communicate with each other. The sharedRAM is located in analogue sampling board.
But during implementation, we found that if the serial port data transfer clock rate is increased, for example, from 1.25Mhz to 2.5MHz, the data we have read from DMA destination address is dislocated. For example, the data should have been the third channel, it actually goes to the first channel, the data should have been in the fourth channel, it actually goes to the second channel, and so on...
This issue becomes serious when the clock rate is increase more, for example. from 1.25MHz to 5MHz (Please refer to attached picture, the CLKR0 is surrounded by a blue box).
Could anyone give me some help? Thanks.
