Part Number:AM5746
Hello, TI Experts,
Our customer sent us a question about GPMC of AM5746.
They create the bus cycle image chart to clarify the wait signal sampling point based on the description in TRM(SPRUIH8) below.
(Please refer attached pdf)
TRM(SPRUIH8): www.ti.com/.../spruih8.pdf
”15.4.4.8.3.1.1 Wait Monitoring During Asynchronous Read Access”
"Figure 15-60. Wait Behavior During an Asynchronous Single Read Access"
”15.4.4.8.3.1.2 Wait Monitoring During Asynchronous Write Access”
Question:
They would like to confirm with attached pdf as below;
- The wait signal sampling start point is two GPMC_FCLK clock cycles before RDACCESSTIME/WRACCESSTIME.
- The wait signal level is ignored before three GPMC_FCLK clock cycles before RDACCESSTIME/WRACCESSTIME.
Is this understanding correct?
We would appreciate if you consider to check the attached pdf.
Best regards,
(Please visit the site to view this file)