Part Number:AM5726
Hi Champs,
We believe DDR3 ODT is able to set bellow register.
My question , when we enable ODT using this resistar, Is this ODT statement always ENABLE during EMIF and DDR3 comunication ?
Do you have some case of "Disable" statement during DDR3 comunication ?
If it happen sometimes "disable" statement at DDR communication, does it have any register to continue always ODT "ENABLE" during DDR communication ?
Regards,
Kaz