Part Number:AM3352
Hello,
I'm reading the post #2 by peaves in the original thread.
Q.
It sounded to me that the McSPI data receiver circuit is clocked by --- Not the Output clock, But the actual SPIx_SCLK voltage. Is it correct?
Q.
Could you please tell me what timing spec will be affected by the SLEWCTRL bits? In other words, could you please relate the (TRM SLEWCTRL bits) and (DS McSPI Master Mode Timings)?
As background, my customer problem was solved by the SLEWCTRL bits. So we are investigating whether the solution was reasonable or not.