Part Number:OMAP-L138
Hi,
We have an OMAP-L138 processor, whose DSP has a uPP interface with an FPGA.
So far, we have been working at a clock rate of 300 MHz (which makes the uPP module and transmit clocks 150 MHz, according to the Technical Reference Guide and the Clock Calculator Excel sheet), and our interface with FPGA was working properly.
Recently, we have switched to a new board that supports the 456-MHz setting, so we changed the PLL controllers such that the DSP is now running at 456 MHz (which makes the module clock 228 MHz (fixed ratio, cannot be changed), but we maintain the transmit clock at 150 MHz). In this setting, when sending data from the DSP to FPGA, uPP occasionally throws a "Channel Q underrun/overflow interrupt", which would never occur at 300 MHz.
Our uPP clock divider value (in the UPICR register) is originally:
CLKDIVA = 3; // which should divide the transmit clock by (2 * (3 + 1))
CLKDIVB = 2; // likewise, by (2* (2 + 1))
But I don't know how to reduce the transmit clock back to 150 MHz in the 456-MHz setting. (I tried raising the clock dividers A and B up to 10, but that did not make a difference since, obviously, they do not affect the module clock).
What do you suggest?
Thanks in advance,
Silacko