Part Number:OMAP-L138
In OMAP L138, ARM,DSP,EDMA controller and memories and all peripherals are interfaced through SCR so my quation is that while EDMA memory access is happening means control of memory buses is with EDMA controller so that time ARM or DSP will be executing or they will be in halt state (wait state) and if they are not in wait state then how parallel accesses are happening while EDMA ,ARM,DSP all are working at same time?