Part Number:OMAP-L138
The wait signal is indicated as required in table 33-5 (Section 33.2.5) of SPRUH77C.
* If this flow control is not needed, can this pin be omitted during PINMUX configuration?
As I understand it each channel has a 512 byte FIFO. If a channel operated in 8/16 bit mode, I assume this FIFO can hold up to 512/256 samples respectively.
* Is this correct?
Our application uses A & B channel in 8/16 bit RX mode. An FPGA supplies an enable signal to control data reception.