Part Number:OMAP-L138
I am looking at an (inherited) design using the OMAP-L137 with a 16-bit parallel ADC.
As there doesn't appear to be any way that the L137 interfaces seamlessly to a parallel ADC, the ADC pins have been connected to GPIO pins, including one GPIO pin which is used to trigger a HWI when the ADC data is ready. This means that I need to call a HWI on a per sample basis.
I was trying to find out what kind of overhead would be incurred by each of these HWIs and found SPRAAX9, which is not related to this processor (is for C2800), but does give information about the interrupt overheads. If I am reading it correctly, it seems to be suggesting that for a HW Interrupt within DSP/BIOS, there would be an overhead of 217 cycles per HW interrupt, increasing to over 1000 cycles overhead if my HWI posts a semaphore. Doing a HWI outside the RTOS would reduce the number to 16 cycles.
This would seem to hugely impact the maximum rate at which my ADC would be able to run.
Are equivalent numbers available for the OMAP-L137 ? If not, are the numbers going to be in the same ballpark ?
Also, is this actually the best way to connect a parallel ADC to the L137?
Could a move to the L138 take away much of the overhead by processing the samples through the UPP?
Thanks and regards
Lorraine