Part Number:OMAP-L138
Hi,
I have a question about the behavior of ECC_STATE in NANDFSR register of NAND controller of OMAP-L138.
Is it correct that understanding that after setting the 4BITECC_ADD_CALC_START bit to 1,
ECC_STATE changes to 4 or more after a short time, and finally transits to 0-3 value?
Depending on the fast timing, 0 may be read from ECC_STATE, so I asked a question.
Best Regards,
Miyashiro