Question about PCB impedance of OMAP-L138

Hi,

My customer is suffering, so I want to your help.

Table 6-29(P139) of the datasheet shows the DDR2 memory pattern constraint Single-ended impedance Zo is described as 50 to 75 Ω, but there is no description about differential impedance.

I think that the DDR_CLKP and DDR_CLKN lines are differential signals, are there restrictions on the differential impedance to be adjusted with the pattern?
(For example, if Zo = 60 Ω, can it be 2 x Zo = 120 Ω ?)

Also, is it OK to recognize that the terminating resistance is unnecessary?

Please give me if you have any information.

Best Regards,
Miyashiro