Hello,
I want to understand recovery process when FIFOFULL is occurred. I see a phenomenon which is out of alignment about data after I re-initialize UPP due to FIFOFULL. UPP is receive mode. UPP uses START pin from FPGA. I understand system priority is important. I just want the method of recovery process.
It seems like UPP FIFO doesn't receive the following data when FIFOFULL is occurred. Then I re-initialize UPP. It's processed by 29.2.6.1 Step-by-Step Procedure in TRM. During the time, FPGA doesn't send data. After that UPP waits to receive next window. I want UPP to receive and send to new address of DDR2. But UPP sends data to continued previous address. How do I quit DMA for previous transfer? Please give me some advice.
Regards,
Kazu