Hi.
We have a custom OMAPL-132 board with Micron NAND MT29F1G08ABBDAHC. On some of our boards we encountered nand read and bad blocks failures. We currently have the nand partitioned with UBIFS, JFFS2 partitions and raw data.
I have a few questions that is unclear to me:
1) Subpages, Is there support for it? In the code i can see that it is supported (uboot and kernel), but in 
It says subpages are not supported. What is right then??
2) ECC: What is the correct mode HW_ECC_OOB_FIRST or just HW_ECC? i saw nowhere a reference for the difference and when to use each of them
3) Layout: L-132 Reference Manual says it supports 4-bit Reed-Solomon ECC code, Micron page here: 
says that 72 bits (for 512 bytes i assume) are needed. That makes 9bytes*4areas = 36 bytes for ECC. Another 8 bytes i reserve for JFFS2, now what about the bad block marker? Page 73 in Micron datasheet shows a spare area layout with 2 reserved bad block bytes per 512 bytes. That sounds weird, shouldn't it be like this only when using on-die ECC is used and in my case bad-block table should be stored in last page of nand? So i am a bit of confused on what the correct layout should be... Page here says
For SLC large page (2112-byte/1056-word page) devices, any block where the first and sixth bytes (x8 device)/first word (x16 device) in the spare area of the first page does not contain FFh is a bad block.
So how do i implement this in u-boot / kernel code?