We use the UART1 of an L138(DSP part) to communicate with a host PC (115200@8N1).
Packets have 1kByte and are sent once a second to the PC and received
about once a minute from the PC.
The DSP of the L138 services the UART via interrupts.
The link to the host is working fine as long as only one interrupt
(either Receiver Data Ready (RDR) or Transmitter Holding Register Empty
(THRE)) occurs.
When both events occur at the same time, it happens sometimes that the
UART stops signaling interrupts.
It seems that the THRE interrupt is cleared when a RDR interrupt is read,
so we changed the ISR to service the THRE by polling.
The ISR serves reads the IIR-register and executes the RDR and timeout-ints.
After that we poll the LSR-register to see if there is space in the TX-FIFO.
It works much better now, but did not solve the problem completely.
Still the UART hangs once in a while, when both interrupts occur at the same time.
We think that it is the same reason here:
e2e.ti.com/.../274366
Now the questions:
Has anyone a bullet proof solution to this problem?
Is there any recommendation from TI how to serve the UART interrupts correctly?
Thanks,
Alex
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