I use CPU poll to transmit data to UART, something like following code in a loop:
if(uart2Regs->LSR & 0x20) { CSL_FINS(uart2Regs->THR, UART_THR_DATA, data); }
Now I want to change this to EDMA than can transmit N bytes:
- I start the EDMA transmit by CPU while THRE in LSR is 1 .
- the EDMA copy one byte to THR. THRE will be cleared to 0.
- Everytime THRE in LSR changed from 0 to 1, the EDMA copy 1 byte to THR.
- repeat step 3 for N-1 bytes.
Here is the UART document about DMA
Activity in DMA channels can be synchronized to these events. In the non-FIFO mode, the UART
generates no DMA events. Any DMA channel synchronized to either of these events must be enabled at
the time the UART event is generated. Otherwise, the DMA channel will miss the event and, unless the
UART generates a new event, no data transfer will occur.
I can't understand the document, If no DMA events is generated in non-FIFO mode, how can the EDMA transmit data
synchronized to these events?