AM1808 USB 2.0 Bulk IN Transactions - Clearing TXPKTRDY bit

Hi, 

I have a question about AM1808 USB 2.0 Controller.

I'm using AM1808 USB 2.0 as Bulk In Transactions.
I want to know when the TXPKTRDY be cleared by USB Controller.
In TRM(spruh82a) page.1588 "34.2.7.1.2.1.2 Operation", it said as following:
/////////////////////////////////////////////////////////////////////
When the packet has been sent, the TXPKTRDY bit will be cleared by 
the USB controller and an interrupt generated so that the next packet
can be loaded into the FIFO.
/////////////////////////////////////////////////////////////////////

After sending the packet, does USB controller clear TXPKTRDY bit 
after receiving ACK from the Host?

Or does USB Controller clear TXPKTRDY bit as soon as PACKET is sent 
regardless of ACK from a host?

best regards,
g.f.