Data dropped on SPIDAT1

I am looking to transmit 3 frames of 8-bits each. The 3 frames are sent during one CS cycle. I am using a lossy transmission wire, and would like to slow down the speed of my transmission.When I apply any prescaler >=4, the second 8-bit frame gets dropped. I wish to set the prescaler to 0x32.

Here are scope images of the OMAP L138 LCDK with prescaler=3 and prescaler=4, respectively:

Prescaler=3 : 

Prescaler = 4:

CH1=CLK

CH2=CS

CH3=SPI0_SIMO

What is the reason that bits in the middle frame get dropped when prescaler>=4? For reference, here are some relevant excerpts from my code.

char reset_frame_register= 0x00;
char reset_frame_b15to8= 0xFF;
char reset_frame_b7to0= 0x83;

Spi_send(reset_frame_register,reset_frame_b15to8,reset_frame_b7to0);

/*------------------------------------------------------------------------------
* static void Spi_send(char one, char two, char three)
------------------------------------------------------------------------------*/
/*
*
*  @Param1 : char frame_b23to16
*  @Param2 : char frame_b15to8
*  @Param3 : char frame_b7to0
*  @RetVal : None
*
*  @Description : This function writes three 8-bit frames during one CS cycle
*
*/
static void Spi_send(char frame_b23to16, char frame_b15to8, char frame_b7to0)
{
	//Turn on CSHOLD & put data on simultaneously
		//Below is equivalent of CSL_FINS for two fields simultaneously - Setting CSHOLD and PUTTING NEW DATA
	(spiRegs->SPIDAT1) = (
							(
								 (
									(spiRegs->SPIDAT1) & ~CSL_SPI_SPIDAT1_CSHOLD_MASK
								 )| CSL_FMK(SPI_SPIDAT1_CSHOLD, 0x01)
							 )& ~CSL_SPI_SPIDAT1_TXDATA_MASK
						 )| CSL_FMK(SPI_SPIDAT1_TXDATA, frame_b23to16);

	//Keep CSHOLD state, drop new data onto pins
	CSL_FINS(spiRegs->SPIDAT1,SPI_SPIDAT1_TXDATA,frame_b15to8);

	//Turn off CSHOLD (CS goes high after the following data is done being transferred
		//Below is equivalent of CSL_FINS for two fields simultaneously - Clearing CSHOLD and PUTTING NEW DATA
	(spiRegs->SPIDAT1) = (
							 (
								 (
									(spiRegs->SPIDAT1) & ~CSL_SPI_SPIDAT1_CSHOLD_MASK
								 )| CSL_FMK(SPI_SPIDAT1_CSHOLD, 0x00)
							 )& ~CSL_SPI_SPIDAT1_TXDATA_MASK
						  )| CSL_FMK(SPI_SPIDAT1_TXDATA, frame_b7to0);
}

//SPIFMT configuration
spiRegs->SPIFMT[0] = CSL_FMK(SPI_SPIFMT_CHARLEN,SPI_NUM_OF_TXBITS)
                       | CSL_FMK(SPI_SPIFMT_WDELAY,0x00) //(0-3Fh)Instroduces a delay (WDELAY*P_SPI_module_clock + 2*P_SPI_module_clock)
                       | CSL_FMK(SPI_SPIFMT_PRESCALE,0x4) // 2h-FFh. Scales the clock SPIx_CLK frequency = [SPI module clock] / [SPIFMTn.PRESCALE + 1]
                       | CSL_FMK(SPI_SPIFMT_POLARITY,CSL_SPI_SPIFMT_POLARITY_LOW) //CLK Polarity is LOW before data begins sending
                       | CSL_FMK(SPI_SPIFMT_PHASE, CSL_SPI_SPIFMT_PHASE_DELAY ); //CLOCK begins quarter cycle after DATA and CS