FPGA Spartan-6 is connected to DSP C6748 by uPP bus. FPGA creates the readiness signal which used to interrupt the DSP, i.e. DSP call to uPP driver to transfer data from FPGA into DSP.
So, what the duration of data availability from time of readiness signal appearance till the moment of data load by FPGA should I set up to allow the uPP driver to access the data? Is there any critical requirements?
Datasheet did not give me an answer for this question.
I will appreciate for answer.