We have configured McBSP to use FIFO and linked EDMA to handle the transfers. Buffer size is 64 byte. Data transfer is happening between two c674x processors. No loss of data or errors observed in communication.
Configuration is : Frame sync at every 130usec. Data occupies 80usec between two frame syncs (all 64 bytes gets transmitted in 80usec)
EDMA configured to copy 64bytes for 1 event.
But, there is a delay between, when the packet is originated and when the same packet received. And this delay is more than expected.
Expected delay is 260 +/- 50usec. But actual delay is observed to be around 800usec.
This delay is measured in EDMA isrs in each DSP by triggering signals on GPIOs of each processor.
My conclusion is that, its FIFO is causing this delay.
Here FIFO size is 256 bytes, WNUMEVT is 64 bytes.
When an EDMA event occurs, it copies set of 64 bytes to McBSP, but McBSP FIFO has 192 bytes (256-64) in its queue which before this new set can go out of McBSP.
To verify this: I disabled FIFO in McBSP and reconfigured EDMA. Delays are as expected.
Now the question is, how to avoid this delay when FIFO is enabled in McBSP.