Part Number:66AK2G12
Hello,
I'm connecting 4 DDR3 8 bit and 1 DDR3 8 bit by fly by topology. I have two questions:
1. Below the data bus connection from the EVM:
There aren't match between the numbering of the DDR_DQ* lines to DDR3_D* lines. for example DDR3_D01 connected to DDR_DQ2, DDR_D02 connected to DDR_DQ7, I'm not sure why is that. my logical connection is DDR_D02 to DDR_DQ2 and etc'.
2. Referring to the DDR3 Design Requirements for KeyStone Devices, PCB routing for the Address Command Control, in the layout guidelines under section 6.3.1.4 I saw a difference table for Address, Command and Control, usually from what I know the DDR Clock referred to All of them, so the skew is DDR clock to the Address, Command and Control, is that right?
3. I didn't find any info what is the skew/propagation delay between the DDR devices since they are connected in Daisy chain (not relevant for the Data lines). all I see is the table that regarding to specific group.
Thanks for the help.
Snir