Part Number:AM3352
Hi Champs,
I would like to confirm this AM3352 data sheet
http://www.ti.com/lit/ds/sprs717k/sprs717k.pdf
Table 7-24. GPMC and NOR Flash Switching Characteristics—Synchronous Mode has three "F15".
Each of F15 parameter has following Note.
(11) First transfer only for CLK DIV 1 mode.
(12) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(13) Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK.
<Question 1 >
Could you please explain what is "CLK DIV 1 mode" meaning on the above (11) , (12), (13) ?
Is this same as "GPMCFCLKDIVIDER" =1h mean ?
<Question 2>
If "CLK DIV 1 mode" indicate GPMCFCLKDIVIDER＝1h,
we use GPMCFCLKDIVIDER =0h. So, Is this meaning NOT "CLK DIV 1mode" ?
Then, we have to apply above (13) ,right ?
If everything correct , we don't need refer all three F15 comment.
we can look into only one F15 with note 13, right ?
<Question 3>
We didn't understand this note (13) exact meaning.
(13) Half cycle of GPMC_CLK_OUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLK_OUT divide down from GPMC_FCLK.
F15 comment is "Delay time, gpmc_clk falling edge to gpmc_ad[15:0] data bus transition"
So, this "Delay time" is half cycle of GPMC_CLK_OUT that divide down from GPMC_FCLK, is this correct ?
<Question 4>
Page 134 showed timing parameter.
According to this graph, this gpmc_ad[15:0] D1, D2, D3 delay output indicate gpmc_clk "rising edge".
If we would like to apply above F15 with note 13 , this delay output indicate "failing edge".
So, in this case, Is this bellow picture a wrong ? Instead of this , customer apply "gpmc_clk failing edge ?
