Query on OMAP L137 SDRAM configuration registers

Hi,

I have few queries on OMAP L137 SDRAM configuration registers:

1) SDRAM Configuration Register (SDCFG):  SDREN [BIT16]

The reference manual states that, when SDREN bit is reset [0],

0 ---> SDRAM initialization and refreshes disabled, but SDRAM write/read transactions allowed.
         This bit must not be cleared to 0 when EMIFB is in self-refresh state.

Can you please elaborate on this. If i reset this bit then how the control signal works to handle the read/write transactions. 

2) Is there any way to disable the Burst mode in the SDRAM.

I did not find any dedicated register to handle it other than the below information. Which by default set by NM bit value in SDCFG register.

From "21.2.6.4 SDRAM/mobile SDRAM Auto-Initialization Sequence"
If NM = 0, EMB_A[2:0] = 2h (CAS latency = 2) (Burst Length = 4)
If NM = 1, EMB_A[2:0] = 3h (CAS latency = 3) (Burst Length = 8) 

Please let me know.

Thanks & Regards
Srinivas