Part Number:66AK2G12
I am bringing up a McASP interface on a new design and have successfully obtained correct Tx output data from the McASP when written by the C66 DSP under software control. Moving on, I wish to service the McASP by EDMA and I have got to the point where the DMA appears to be operating and Tx frame sync pulse are appearing (using burst mode), however the Tx data is apparently all-zeros. The DMA is reading from a simple memory array in C66 L2 SRAM and writing to the McASP via the DATA port. The EDMATC_ERRSTAT register is indicating a bus error and the EDMATC_ERRDET register indicates that this is associated with the read cycle. I have read that if the read fails then the DMA transfer will still progress but with zero data, which appears to agree with my observations.
My question is, what are the possible causes of the read failure as I am running out of ideas? I have considered memory protection and the DMA is configured to use Supervisor privilege in the OPT field, however I am uncertain if this is sufficient (I have not configured any other specific considerations in respect of the MPU - in fact I am not interested in memory protection at this time and would prefer that all masters have access to everything for the moment).
