Part Number:AM3352
hi team,
As shown below,
When the I/O has a voltage before the AM3352 starts,
The normal board power-on sequence will have a VDD_MPU voltage that is established earlier than VDD_3V3A (About 2.8ms earlier).
But it can start normally.
What is the timing associated with the internal mechanism of the chip?
If the VDD_MPU voltage is established earlier than VDD_3V3A, how long does it take for the problem to occur?
my power suply not use PMIC, my power stage you can reference link as below :
https:// e2e.ti.com/support/processors/f/791/t/791733
my question is
1.when am3352 is not start up, the I/O pin have high volt about 1.1V, what's the problem with this?
2.As you mentioned, If any voltage is applied to the I/O pins of the processor while it is powered off then that may damage the I/O pins and leave them not functional.
What is the internal mechanism of the chip?
3.If it is a problem caused by Power-Supply Sequencing, is there a definition of how many time intervals will an exception occur?
There are only schematic on the specifications.
thanks.