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66AK2H14: Throuhgput or communication example?

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Part Number: 66AK2H14

Hi Eric,

I´m loking for a solution using any TI´s kit (DSP or ARM) to read voltage signals of a grid and send to a remote host in a industrial network. 

I´ve bought some hercules´s kits, two AM437x Industrial dev kit, two AMIC110 Industrial Communications Engine and if need I´ll look other kit to solve my problem. 

After some reading and search, I think the solution to implement the comunication is use the lwIP library. Am I corret? Or are there other away? My first test is with hercules dev kit.

Do you have any simple example implementing UDP, TCP, or socket using lwIP with hercules? Or with some related kits (hercules, AM437x or AMIC110)?

Thanks,

Geraldo.


AM3354: AM3354 GPMC AD Multiplexed Upper Address Lines

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Part Number: AM3354

I'm using the AM3354 (ZCZ package) GPMC to connect to an external device using AD Multiplexed mode, and need more than 16 address lines available on GPMC_AD0..GPMC_AD15.  I've read through a number of threads here, as well as the TI specifications SPRUH73P, and SPRS717J.  I haven't found a clear, definitive answer to my question.  SPRUH73P Table 7-5, Figure 7-3, Figure 7-43 are inconsistent in their address line naming.

What I need to know, specifically, is which are the subsequent address PINS to use after GPMC_AD15.  For a specific, simple example, when incrementing from address "0x000FFFE" to "0x0010000", from the CPU software point of view, which GPMC pin represents the upper address line that just changed from 0 to 1?  Some of the GPMC_Ax signals are available on multiple pins, and some are dual purpose (e.g. R13 can be either GPMC_A0/GPMC_A16, according to SPRS717J)

Here is my planned pin usage, I'd like to know if the upper address lines are correct, and if pin R13 is the next address line beyond pin U13 (GPMC_AD15).

ZCZ AD Multiplexed Pins (Only showing some, as there is only one pin option for this set)

  • GPMC_AD0 -> U7
  • GPMC_AD1 -> V7
  • GPMC_AD2 -> R8
  • GPMC_AD3 -> T8
  • ...
  • GPMC_AD15 -> U13

ZCZ Upper Address Pins:

  • GPMC_A0/GPMC_A16 -> R13
  • GPMC_A1/GPMC_A17 -> V14
  • GPMC_A2/GPMC_A18 -> U14
  • GPMC_A3/GPMC_A19 -> T14
  • GPMC_A4/GPMC_A20 -> R14
  • GPMC_A5/GPMC_A21 -> V15
  • GPMC_A6/GPMC_A22 -> U15
  • GPMC_A7/GPMC_A23 -> T15
  • GPMC_A8/GPMC_A24 -> V16
  • GPMC_A9/GPMC_A25 -> U16
  • GPMC_A10/GPMC_A26 -> T16
  • GPMC_A11/GPMC_A27 -> V17

threads here that indicate "Mode 0" actually needs to be used when in the AD-Multiplexed configuration.

Thanks,

-Paul

TDA2P-ACD: Using dual UB962 for 8 cameras (csi2 ports only)

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Part Number: TDA2P-ACD

Hi, ALL.

We're planning to connnect 8 cameras to TDA2P-ACD using only csi-ports (csi_0 with 4 DL config and csi_1 with 2 DL config), please, see picture below.

(1) Is it possible to connect 8 cameras using both csi-ports only (with dual UB962)?

(2) We already tested UB962 with TDA2P using only csi_0 port in 4 DL mode. It works fine with 4 cameras!
Now we want to try UB962 (4 cameras) with csi0_port in 2 DL mode.
Which steps we need to do for using 2 DL connection?
We have problems.
Here is sample vision_sdk code. We changed '_4LANES' constant to 'SYSTEM_VIFW_2LANES', but 4 blank screens was observed.

{SENSOR_SONY_IMX224_CSI2,
        {1u,{0x36,0x37,0x38,0x39},{ 0x20, 0x21, 0x22, 0x23 }, TRUE, SYSTEM_VIFW_2LANES, SYSTEM_VIFM_SCH_CSI2,
            SYSTEM_CSI2_RAW12 /* CSI2 DataFormat*/, 0 /*Virtual Channel Id*/,0, /* IsCSIPostEnable Required */
                {TRUE /* isCplxCfgValid */,
                    {{FALSE, 2u}, /* Clock Lane */
                     {FALSE, 1u}, /* data1Lane */
                     {FALSE, 3u}, /* data2Lane */
                     {TRUE, 4u}, /* data3Lane*/
                     {FALSE, 5u}},/* data4Lane */
                     800u /* csi2PhyClk */ }}},
WriteI2C(UB962, 0x33, 0x35); /* .CSI_CTL, CSI_ENABLE (Enabled), CSI_CONTS_CLOCK (Enabled), CSI_ULP (0x00), CSI_LANE_COUNT (Using 2 Lanes), */

Then we tried to change '800u' csi2PhyClk to '1600u' (or to '1200u)'. But any value greater than 1000 causes an assertion failure in 'DDR_check' code, see below. (1ns check)

    /* Get DDR clock period in nS */
    ddrClkPeriod = (Float32)((Float32)csi2Clk * (Float32)1000000U);
    ddrClkPeriod = (Float32)((Float32)1U / ddrClkPeriod);
    ddrClkPeriod = (Float32)(ddrClkPeriod * (Float32)1000000000U);
    GT_assert(VpsHalTrace, ((uint32_t)ddrClkPeriod > 0U));
    temp    = ((Float32)20U / ddrClkPeriod);
    thsTerm = (uint32_t)temp;

Is it possible to configure TDA2P csi-port in 2 datalane mode using UB962?

Thanks in advance.
Best regards.

LM3S2B93-IBZ80-A2T vs LM3S2B93-IBZ80-C5T

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Hello,

Im trying to figure out the difference between  LM3S2B93-IBZ80-A2T and LM3S2B93-IBZ80-C5T.

Based on the part numbering C5 stands for a higher revision. But I cant find the exact difference. Do you have supporting documents on hand which could help to find out the difference?

Both versions are obsolte.

rgds

Jakob

AM5K2E02: Max Operating Junction Temperature (TjMax)

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Part Number: AM5K2E02

Hi Team,

My Customer wanted to know the Max Operating Junction Temperature (TjMax) of AM5K2E02, do we have this value?

Regards,
_Renan

SDK_VISION RVC on HDMI TDA76P

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HI Rishabh,

I have the same issues here we are using vsdk to implement rvc application usecase for   our custom board based on tda76p, i did all the changes and patches that TI provided us , but untill now , the hdmi display don t shows any think at boot up , i saw in this post that we should add custom board and reconfigure the I2C instance please can you provide us how to do that ? . also i give you the  traces on ipu2 and dsp1 below :

cat /d/remoteproc/remoteproc1/trace0

[0][ 0.000] 18 Resource entries at 0x99000000
[0][ 0.000] 0.427591 s: SYSTEM: System Common Init in progress !!!
[1][ 0.001] [t=0x000a6f09] ti.ipc.family.vayu.VirtQueue: vring: 0 0x60000000 (0x3000)
[1][ 0.001]
[1][ 0.001] [t=0x000aab3c] ti.ipc.family.vayu.VirtQueue: vring: 1 0x60004000 (0x3000)
[1][ 0.001]
[1][ 0.002] [t=0x000ac52e] ti.ipc.family.vayu.VirtQueue: VirtQueue_startup: VDEV status: 0x0
[1][ 0.002]
[1][ 0.002] [t=0x000ad8a5] ti.ipc.family.vayu.VirtQueue: VirtQueue_startup: Polling VDEV status...
[1][ 0.002]
[0][ 0.010] 0.437015 s: SYSTEM: IPC init in progress !!!
[0][ 0.010] 0.437290 s: SYSTEM: Attaching to [DSP1] ...
[0][ 0.013] 0.439882 s: SYSTEM: Attaching to [DSP1] ... SUCCESS !!!
[0][ 0.013] 0.440218 s: SYSTEM: Notify register to [DSP1] line 0, event 15...
[0][ 0.013] 0.440553 s: SYSTEM: Notify init done !!!
[0][ 0.015] 0.442475 s: SYSTEM: MsgQ init done !!!
[0][ 0.015] 0.442719 s: SYSTEM: IPC init DONE !!!
[0][ 0.024] 0.450863 s: SYSTEM: System Common Init Done !!!
[0][ 0.024] 0.451198 s: SYSTEM: System Init in progress !!!
[0][ 0.024] 0.451412 s: SYSTEM: BSP Common Init in progress !!!
[0][ 0.024] 0.451625 s: SYSTEM: BSP Common Init Done !!!
[0][ 0.025] 0.451839 s: SYSTEM: BSP Platform Init in progress !!!
[0][ 0.025] 0.452144 s: SYSTEM: BSP Platform Init Done !!!
[0][ 0.025] 0.452357 s: SYSTEM: FVID2 Init in progress !!!
[0][ 0.025] 0.452662 s: SYSTEM: FVID2 Init Done !!!
[0][ 0.026] 0.452876 s: SYSTEM: VPS Init in progress !!!
[0][ 0.026] 0.453120 s: SYSTEM: VPDMA Descriptor Memory Address translation ENABLED [0x80000000 -> 0x80000000]
[0][ 0.029] 0.456414 s: *** VPDMA Firmware Loading... ***
[0][ 0.029] 0.456688 s: VPDMA Firmware Address = 0xa035aec0
[0][ 0.030] 0.456993 s: VPDMA Load Address = 0x4897d004
[0][ 0.030] 0.457237 s: VPDMA Firmware Version = 0x4d0001b8
[0][ 0.030] 0.457481 s: VPDMA List Busy Status = 0x00000000
[0][ 0.030] 0.457695 s: *** VPDMA Firmware Load Success ***
[0][ 0.030]
[0][ 0.031] 0.458244 s: *** VPDMA Firmware Loading... ***
[0][ 0.031] 0.458488 s: VPDMA Firmware Address = 0xa035aec0
[0][ 0.031] 0.458732 s: VPDMA Load Address = 0x4899d004
[0][ 0.032] 0.459006 s: VPDMA Firmware Version = 0x4d0001b8
[0][ 0.032] 0.459250 s: VPDMA List Busy Status = 0x00000000
[0][ 0.032] 0.459464 s: *** VPDMA Firmware Load Success ***
[0][ 0.032]
[0][ 0.033] 0.460013 s: *** VPDMA Firmware Loading... ***
[0][ 0.033] 0.460257 s: VPDMA Firmware Address = 0xa035aec0
[0][ 0.033] 0.460470 s: VPDMA Load Address = 0x489dd004
[0][ 0.033] 0.460714 s: VPDMA Firmware Version = 0x4d0001b8
[0][ 0.034] 0.460989 s: VPDMA List Busy Status = 0x00000000
[0][ 0.034] 0.461233 s: *** VPDMA Firmware Load Success ***
[0][ 0.034]
[0][ 0.103] 0.529890 s: SYSTEM: VPS Init Done !!!
[0][ 0.104] 0.531842 s: UTILS: DMA: HWI Create for INT25 !!!
[0][ 0.105] 0.532330 s: SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024
[0][ 0.106] 0.532666 s: SYSTEM: Heap = LOCAL_DDR @ 0x00000000, Total size = 262144 B (256 KB), Free size = 259784 B (253 KB)
[0][ 0.106] 0.533184 s: SYSTEM: Heap = SR_OCMC @ 0x00000000, Total size = 0 B (0 KB), Free size = 0 B (0 KB)
[0][ 0.107] 0.533611 s: SYSTEM: Heap = SR_DDR_CACHED @ 0x84203000, Total size = 346030080 B (330 MB), Free size = 346030080 B (330 MB)
[0][ 0.107] 0.534191 s: SYSTEM: Heap = SR_DDR_NON_CACHED @ 0xa0100000, Total size = 1047040 B (0 MB), Free size = 1038592 B (0 MB)
[0][ 0.107] 0.534679 s: SYSTEM: Initializing Links !!!
[0][ 0.293] 0.720124 s: SYSTEM: Initializing Links ... DONE !!!
[0][ 0.296] 0.723723 s: BOARD: Board Init in progress !!!
[0][ 0.297] 0.724333 s: BOARD: Board Init Done !!!
[0][ 0.308] 0.735496 s:
[0][ 0.317] 0.744128 s: dispcore/src/vpscore_dctrl.c @ Line 1934: 0.744342 s: vpscore_dctrlHdmiPowerOn(&hdmiConf)ahmed printVPS_DCTRL_DSS_VENC_HDMI= 8
[0][ 0.385] 0.811779 s: DISPLAY: Create in progress !!!
[0][ 0.386] 0.812816 s: DISPLAY: Create Done !!!
[0][ 0.386] 0.813212 s: GRPXSRC: Create in progress !!!
[0][ 0.418] 0.844811 s: GRPXSRC: Create Done !!!
[0][ 0.418] 0.845269 s: DISPLAY: Create in progress !!!
[0][ 0.419] 0.846153 s: DISPLAY: Create Done !!!
[0][ 0.420] 0.847190 s: SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1023
[0][ 0.420] 0.847526 s: SYSTEM: Heap = LOCAL_DDR @ 0x00000000, Total size = 262144 B (256 KB), Free size = 256904 B (250 KB)
[0][ 0.421] 0.848044 s: SYSTEM: Heap = SR_OCMC @ 0x00000000, Total size = 0 B (0 KB), Free size = 0 B (0 KB)
[0][ 0.421] 0.848502 s: SYSTEM: Heap = SR_DDR_CACHED @ 0x84203000, Total size = 346030080 B (330 MB), Free size = 342091776 B (326 MB)
[0][ 0.422] 0.849051 s: SYSTEM: Heap = SR_DDR_NON_CACHED @ 0xa0100000, Total size = 1047040 B (0 MB), Free size = 1038592 B (0 MB)
[0][ 0.422] 0.849600 s: CHAINS: Sensor create in progress
[0][ 0.423] 0.849844 s: VIDEO_DECODER: ********** CREATE **********
[0][ 0.423] 0.850149 s: src/bsp_boardTda2xx.c @ Line 865: 0.850332 s: ahmed BSP_BOARD_CUSTOM device !!
[0][ 0.424] 0.850576 s: src/bsp_boardTda2xx.c @ Line 877: 0.850759 s: ahmed BSP_BOARD_CUSTOM boardData->numDev== 0 !!
[0][ 0.424] 0.851094 s: src/bsp_boardTda2xx.c @ Line 865: 0.851277 s: ahmed BSP_BOARD_CUSTOM device !!
[0][ 0.424] 0.851521 s: src/bsp_boardTda2xx.c @ Line 877: 0.851704 s: ahmed BSP_BOARD_CUSTOM boardData->numDev== 0 !!
[0][ 0.425] 0.852010 s: src/bsp_board.c @ Line 482: 0.852162 s: ahmed Invalid device driver ID!!
[0][ 0.425] 0.852437 s: src/bsp_boardTda2xx.c @ Line 865: 0.852589 s: ahmed BSP_BOARD_CUSTOM device !!
[0][ 0.426] 0.852833 s: src/bsp_boardTda2xx.c @ Line 877: 0.853047 s: ahmed BSP_BOARD_CUSTOM boardData->numDev== 0 !!
[0][ 0.426] 0.853352 s: src/bsp_board.c @ Line 515: 0.853504 s: Invalid device driver ID!!
[0][ 0.427] 0.853779 s: src/bsp_boardTda2xx.c @ Line 865: 0.853962 s: ahmed BSP_BOARD_CUSTOM device !!
[0][ 0.427] 0.854236 s: src/bsp_boardTda2xx.c @ Line 877: 0.854419 s: ahmed BSP_BOARD_CUSTOM boardData->numDev== 0 !!
[0][ 0.428] 0.854724 s: src/bsp_boardTda2xx.c @ Line 865: 0.854877 s: ahmed BSP_BOARD_CUSTOM device !!
[0][ 0.428] 0.855182 s: src/bsp_boardTda2xx.c @ Line 877: 0.855334 s: ahmed BSP_BOARD_CUSTOM boardData->numDev== 0 !!
[0][ 0.429] 0.855670 s: src/bsp_boardTda2xx.c @ Line 865: 0.855822 s: ahmed BSP_BOARD_CUSTOM device !!
[0][ 0.429] 0.856097 s: src/bsp_boardTda2xx.c @ Line 877: 0.856280 s: ahmed BSP_BOARD_CUSTOM boardData->numDev== 0 !!
[0][ 0.429] 0.856615 s: CHAINS: Sensor create ... DONE !!!
[0][ 0.430] 0.856859 s: DISPLAY: Start in progress !!!
[0][ 0.430] 0.857134 s: DISPLAY: Start Done !!!
[0][ 0.431] 0.857805 s: DISPLAY: Start in progress !!!
[0][ 0.431] 0.858079 s: DISPLAY: Start Done !!!
[0][ 0.432] 0.858903 s: CALLING Board_deInit
[1][ 11.555] [t=0x0dd0ad39] ti.ipc.family.vayu.VirtQueue: VirtQueue_startup: VDEV status: 0x7

 

cat /d/remoteproc/remoteproc2/trace0

[ 0.000] 25 Resource entries at 0xa1000000
[ 0.000] 0.421704 s: SYSTEM: System Common Init in progress !!!
[ 0.000] 0.421948 s: SYSTEM: IPC init in progress !!!
[ 0.000] 0.422039 s: SYSTEM: Attaching to [IPU2] ...
[ 0.018] 0.439882 s: SYSTEM: Attaching to [IPU2] ... SUCCESS !!!
[ 0.018] 0.440004 s: SYSTEM: Notify register to [IPU2] line 0, event 15...
[ 0.018] 0.440126 s: SYSTEM: Notify init done !!!
[ 0.018] 0.440340 s: SYSTEM: MsgQ init done !!!
[ 0.018] 0.440431 s: SYSTEM: IPC init DONE !!!
[ 0.019] 0.441590 s: SYSTEM: System Common Init Done !!!
[ 0.020] 0.441682 s: SYSTEM: System DSP Init in progress !!!
[ 0.020] 0.442627 s: SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024
[ 0.021] 0.442780 s: SYSTEM: Heap = LOCAL_L2 @ 0x00800000, Total size = 227264 B (221 KB), Free size = 227264 B (221 KB)
[ 0.021] 0.442932 s: SYSTEM: Heap = LOCAL_DDR @ 0x00000000, Total size = 524288 B (512 KB), Free size = 522304 B (510 KB)
[ 0.021] 0.443085 s: SYSTEM: Initializing Links !!!
[ 0.038] 0.460501 s: SYSTEM: Initializing Links ... DONE !!!
[ 0.038] 0.460592 s: SYSTEM: System DSP Init Done !!!
[ 0.302] 0.723723 s: SYSTEM: CACHE: L1P = 32 KB, L1D = 32 KB, L2 = 32 KB ... after boot !!!
[ 0.302] 0.723845 s: SYSTEM: CACHE: L1P = 32 KB, L1D = 32 KB, L2 = 32 KB ... after update by APP !!!
[ 0.424] 0.846580 s: SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1023
[ 0.425] 0.846702 s: SYSTEM: Heap = LOCAL_L2 @ 0x00800000, Total size = 227264 B (221 KB), Free size = 227264 B (221 KB)
[ 0.425] 0.846855 s: SYSTEM: Heap = LOCAL_DDR @ 0x00000000, Total size = 524288 B (512 KB), Free size = 522144 B (509 KB)

 

 

Best Regards 

AHMED

AM3356: UART boot fail

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Part Number: AM3356

on a new customer board, UART boot fail, host send Xmodem package upon receive CCC. captured waveform as below, when host send the first package, target AM335x response with NAK 

Compare with BBB board wave form, AM335x response ACK after the whole package:

Below is customer's SOM board PCB, route out UART0 TX/RX to the post card board edge directly, there is no serial or pull up/down resistor. use USB to UART TTL cable to connect on the solder point(RED) to capture waveform. 

connect with RS232 from base board, same result:

Use logic analyzer to capture the RX signal, the seems add one more bit at each byte.

if use USB to TTL cable, occasionally can boot successfully. the successful waveform captured with logic analyzer as below:

Question:

Any clue to debug this issue?

CCS/OMAP-L137: How to implement simple FIR filter on TMS320C6747/OMAP-L137

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Part Number: OMAP-L137

Tool/software: Code Composer Studio

Hello.

I'm studying ANC algorithm from LG Electronics, and I'm using TMS320C6747/OMAP-L137 DSP  STARTER KIT. 

First, I downloaded OMAPL137 RTOS SDK from http://software-dl.ti.com/processor-sdk-rtos/esd/OMAPL137/latest/index_FDS.html.

After that I used mcasp_test.c example code from C:\ti\pdk_omapl137_1_0_10\packages\ti\board\diag\mcasp\src\mcasp_test.c

I am trying to implement a FIR filter(low pass) on a TMS320C6747

Please see my code below.

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

                 short SampleCh0;
                 short SampleCh1;

                 float RegX1 = 0.0;
                 float RegX2 = 0.0;
                 float RegX3 = 0.0;
                 float RegX4 = 0.0;
                 float RegX5 = 0.0;
                 float RegX6 = 0.0;
                 float RegX7 = 0.0;
                 float RegX8 = 0.0;
                 float RegX9 = 0.0;

                 float RegX1_1 = 0.0;
                 float RegX2_1 = 0.0;
                 float RegX3_1 = 0.0;
                 float RegX4_1 = 0.0;
                 float RegX5_1 = 0.0;
                 float RegX6_1 = 0.0;
                 float RegX7_1 = 0.0;
                 float RegX8_1 = 0.0;
                 float RegX9_1 = 0.0;

                 float b[10] = {FIR filter coefficients};

 

                 ......

                 /*
                 ** Loop forever. if a new buffer is received, the lastFullRxBuf will be
                 ** updated in the rx completion ISR. if it is not the lastSentTxBuf,
                 ** buffer is to be sent. This has to be mapped to proper paRAM set.
                 */
                 while(1)
                 {
                 if(lastFullRxBuf != lastSentTxBuf)
                 {
                 // if(sampleCnt > TEST_SAMPLE_COUNT)
                 // {
                 // break;
                 // }

                 /*
                 ** Start the transmission from the link paramset. The param set
                 ** 1 will be linked to param set at PAR_TX_START. So do not
                 ** update paRAM set1.
                 */
                 parToSend = PAR_TX_START + (parOffTxToSend % NUM_PAR);
                 parOffTxToSend = (parOffTxToSend + 1) % NUM_PAR;
                 parToLink = PAR_TX_START + parOffTxToSend;

                 lastSentTxBuf = (lastSentTxBuf + 1) % NUM_BUF;

                 secondLastSentTxBuf = (secondLastSentTxBuf + 1) % NUM_BUF;

                 SampleCh0=*((void *)rxBufPtr[lastFullRxBuf] + 2 * i );     

                 SampleCh1=*((void *)rxBufPtr[lastFullRxBuf] + 2 * i + 1 );

                /* FIR filter processing */

                for(i = 0; i < NUM_SAMPLES_PER_AUDIO_BUF; i++)
                {
               SampleCh0_1 = b[0]*SampleCh0 + b[1]*RegX1 + b[2]*RegX2 + b[3]*RegX3 + b[4]*RegX4 + b[5]*RegX5 + b[6]*RegX6 + b[7]*RegX7 + b[8]*RegX8 + b[9]*RegX9;
               SampleCh1_1 = b[0]*SampleCh1 + b[1]*RegX1_1 + b[2]*RegX2_1 + b[3]*RegX3_1 + b[4]*RegX4_1 + b[5]*RegX5_1 + b[6]*RegX6_1 + b[7]*RegX7_1 + b[8]*RegX8_1 + b[9]*RegX9_1;
               RegX9=RegX8;
               RegX8=RegX7;
               RegX7=RegX6;
               RegX6=RegX5;
               RegX5=RegX4;
               RegX4=RegX3;
               RegX3=RegX2;
               RegX2=RegX1;
               RegX1=SampleCh0;

               RegX9_1=RegX8_1;
               RegX8_1=RegX7_1;
               RegX7_1=RegX6_1;
               RegX6_1=RegX5_1;
               RegX5_1=RegX4_1;
               RegX4_1=RegX3_1;
               RegX3_1=RegX2_1;
               RegX2_1=RegX1_1;
               RegX1_1=SampleCh1;

               }     

                *((void*)txBufPtr[lastSentTxBuf] + 2 * i) =  SampleCh0_1;
                *((void*)txBufPtr[lastSentTxBuf] + 2 * i + 1) =  SampleCh1_1;

                BoardDiag_BufferTxDMAActivate(lastSentTxBuf, NUM_SAMPLES_PER_AUDIO_BUF,
                (unsigned short)parToSend,
                (unsigned short)parToLink);
                sampleCnt += NUM_SAMPLES_PER_AUDIO_BUF;
                }
}

-----------------------------------------------------------------------------------------------------------------------------------------------------

I separated audio input two channels (SampleCh0, SampleCh1), and applied the FIR filter algorithm.

Please let me know my code is right or not.

PS. I also tried another FIR filtering code example from https://e2e.ti.com/support/processors/f/791/t/409101, but I just heard noise with original input signal from output.

If you have any FIR filter, LMS, filtered-x LMS alogrithm code example, please let me know.

Any help is much appreciated. Thanks.


TMS320C6654: TMS320C6654CZH8

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Part Number: TMS320C6654

Hello,

I am using TMS320C6654CZH8 and now playing some VoIP audio algorithms via the McBSP port. It works fine. The core voltage is 0.98 (With a DVM). The VID code is 1101. It is steady voltage though. Is this normal? Or should the core voltage be constantly be going up and down as requested through VID lines. This is for my understanding. The VID lines don't change and remain at 1101. Ethernet is also working.

Divakar

AM5728: Setting interrupt priority for IPC and my own bare metal ISR installed with Hwi_plug()

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Part Number: AM5728

I had a bare metal design that was pushing data (47Mbyte/sec) from the 4 PRU's (connected to 4 dual ADC's) into the DSP core.

The A15 team developing the main app under Linux gave me the only option of running RTOS and using IPC to communicate with them so now I have that stuff too running on the DSP core.

Now that we have all this integrated, I find that I am missing interrupts from the completion of the DMA events (and losing data).

I believe IPC is using interrupt 3 on the DSP because I had to move my ISR onto interrupt 4 i.e. Hwi_plug(4, DSP_PRU_isr).

I would like to reverse this and use interrupt 3 instead of 4 for my ISR. I believe this would give the DMA interrupts priority over IPC.

Would it be enough just to reserve interrupt 3 somehow in the cfg script for me to use with Hwi_plug()? And, how do I do that?

Do I further need to specify int 4 for IPC? And how?

Will int 3 be able to preempt servicing int 4 (will it jump out of the ISR for int 4 and jump to the ISR for int 3)?

BEAGLEBK: Beaglebone Black changing default device tree configuration for GPIO

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Part Number: BEAGLEBK

Hi,

I have a customized design that is based on Beaglebone Black, but some of GPIOs are changed for other purposes. For example, GPIO2_30 is used as a GPIO input. I modified the device tree in-place in dts/am335x-bone-common.dtsi like below:

mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
                        AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)              /* spio0_cs1.gpio0_6 */

                        ...
                        AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE7)       /* mmc0_clk.gpio2_30 */
                        AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4)              /* mcasp0_aclkr.mmc0_sdwp */
                >;
        };

Question: I know this works, but I wonder what is the typical way (best practice) to modify default device tree for customized GPIOs? The software is built from meta-ti Rocko branch tag "ti2018.03" using Yocto build system.

Thank you for your help.

TPS659413 data sheet

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Hi Engineers

Using J721EX SOMG01 EVM, we are going to make our own board.

To do this i need TPS659413 data sheet, Does anybody can help with this.

BR

Hennessy

PROCESSOR-SDK-AM335X: TMDSSK3358 Board change PMIC issue ( need modify source code or not ? )!!

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Part Number: PROCESSOR-SDK-AM335X

AM335x Starter Kit (TMDSSK3358 Board ) use  PMIC is  TPS65910 

BeagleBone KIT  use PMIC is  TPS65217 

question : 

AM335x Starter Kit (TMDSSK3358 Board )  PMIC chage to   TPS65217  , the (TMDSSK3358 Board) source code need modify ? or not .

thanks'

TDA2SX: TIDL on hlos

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Part Number: TDA2SX

Hi, I  transplant  RTOS  TIDL usecase on HLOS like the picture, and  changge algtidlpreproc   on A15  to DSP1 ,Compile ok,and run  without fail。

but  only the display link  proecess  one time,and  then there is  no Other phenomena。  I   want  to  ask   if    tidl can  run like that。 

(Please visit the site to view this file)

AM5746: TMDXIDK574_SCH

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Part Number: AM5746

Hi Sitara Support Team,

Regarding the comment in TMDXIDK574_SCH.pdf,

does this need to remove for AM574xIDK?
(Please visit the site to view this file)

 *****

Note that ECC use is

highly constrained -

please refer to the

AM572x Errata document

for more information

 *****

Or TMDXIDK574 has still to care about the errata of AM572x?

If my customer will design with AM574x and DDR3 with ECC,

Could he refer to the design of TMDXIDK574 including the schematic?

 

Best regards,
Kanae


TMS320C5517: Does the C5515 FFT errata apply to the C5517 too?

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Part Number: TMS320C5517

The C5515 came with an errata about the FFT ROM routines: "The hwafft_Npts routines available in ROM use pointers to access the data and scratch buffers. These pointers are copied as 16-bit addresses instead of 23-bit addresses when copying from AR0 to AR3 and from AR1 to AR2." The workaround is to ensure that buffers do not cross 16-bit address boundaries.

Is this workaround still required for the C5517, or was the issue fixed?

TDA2EXEVM: Algo SW_mosaic display actual frame is not displying

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Part Number: TDA2EXEVM

Hi,

We are developing an automotive DVR Software using TDA2Sx processor leveraging upon Vision SDK.

We designed the use-case with three functionalities namely recording of .mp4 files, single channel display and Quad display. Totally we are using six analog (CVBS) cameras.
The below is the use-case.
Capture -> VPE -> Dup  -> Encode -> IPCIn(A15) -> DefLink_vsdkbuf (A15)

Dup -> Merge -> Display

Dup -> Sync -> Alg_DmaSwMs -> VPE_D2 -> Merge -> Display
 
We are using Algorithm SW_mosaic for multiple channels(4-channels) in a single frame and then display it. Run time switching between single channel display and  quad display are fine. But in Algo SW_mosaic display actual frame is not displying, actual frame is getting cropped in quad display. But  in single channel display it fine.



It would be very helpful if you could help us, having respective TI support team in providing us with inputs to resolve this issue.

Rgds,

Balaji T

TMDXIDK5718: How to calculate the execution time of a task in M4 core

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Part Number: TMDXIDK5718

Hi,

I was trying to calculate the execution time of a task running inside M4 with bare-metal code(No- OS), how I can do that.

I tried with example provided in C:\ti\pdk_am57xx_1_0_15\packages\ti\csl\example\timer\timer_app\main_m4.c  by using timers, but I am getting huge time period values. And I am getting 120 clock ticks for 2 successive TIMERCounterGet calls, why this much of huge values? Is any thing I am doing wrong?

SYS_CLK1 is the clock signal for the timer and in IDK board it's 20 MHz.

Below are the steps I have followed:

1. Started a timer4 with 60 sec timeout in interrupt mode

2. Reading the TIMERCounterGet before and after the task  execution, and calculating the number of clock ticks for executing the task

3. Calculating the time period from the difference in clock ticks,

time period = (clock ticks * 0.05 Micro sec)

As frequency is 20 Mhz, one clock tick will be 0.05 Micro Sec.

(Please visit the site to view this file)

And one more doubt, as M4 is not supporting Hardware FPU's what is the added delay if I use software FPU library in the application execution time. 

Regards,

Naveen.

AM5706: SD card boot issue

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Part Number: AM5706

Hi,    

A circuit board based on AM5706 is designed.

The power scheme uses TPS65916. The circuit design is basically based on "Entry Level Head Unit Display Audio With JacintoTM 6 Entry Schematic".


The board is designed with a 16-bit DDR3 DRAM, an eMMC (using the MMC2 port, but not soldered), and an SDCARD interface (using the MMC1 port).


After the software engineer makes the UBOOT SD card, configure SYSBOOT[5:0] to 110000, the board cannot be booted from the SD card, and UART3 has no information output.


1.Measure the signal on SDIO and find that only at the moment of power-on, only CLK.CMD, DAT0 has a signal, and then there is no other signal.


2.Remove the SD card, connect to JTAG, use CCS for debugging, you can set breakpoints in main.c.


3.Configure SYSBOOT[5:0] to 010011 and select to boot from UART. You can read continuous "JE! JE!" information at UART3.


Because the entire system is basically a 3.3V power supply, the SDIO signals all use a 3.3V pullup. The AM5706's vddshv8 is also directly connected to 3.3V, and the PMIC TPS65916's LDO1 is suspended.


Because it is the first time to use this chip, the small company has no other support, so the debugging work is stuck, please give pointers.


Thank you!


K2GICE: PCI-e example cable mod

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Part Number: K2GICE

Hi

I have found guide for pcie cable mod for male to male cable but for k2gice I need an female to female cable. I have two riser cables from which to modify these. Have i understo correctly that from this pintout i connect pins 1-1, 2-2 etc but do not connect any power cable and connect transmit lane to reciever lane.

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